📄 bspserial.c
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OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENB_LSH));
break;
case CSP_BASE_REG_PA_UART5:
//Reset UART A
OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_USELA_LSH));
//Disable UART A
OUTREG16(&g_pPBC->BCTRL1_SET, (1 << PBC_BCTRL1_CLEAR_UENA_LSH));
//Disable UART A MODEM
OUTREG16(&g_pPBC->BCTRL2_SET, (1 << PBC_BCTRL2_UMODENA_LSH));
break;
}
}
MmUnmapIoSpace(g_pPBC,sizeof(CSP_PBC_REGS));
}
//-----------------------------------------------------------------------------
//
// Function: BSPUartConfigureGPIO
//
// This function is used to configure the GPIO.
//
// Parameters:
// HWAddr
// [in] Physical IO address.
//
// Returns:
// TRUE if successfully performed the required action.
//
//-----------------------------------------------------------------------------
BOOL BSPUartConfigureGPIO(ULONG HWAddr)
{
BOOL result = FALSE;
PHYSICAL_ADDRESS phyAddr = {HWAddr, 0};
switch (HWAddr)
{
case CSP_BASE_REG_PA_UART1:
DDKIomuxSetPinMux(DDK_IOMUX_PIN_RXD1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_TXD1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_RTS1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CTS1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_DTR_DCE1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_DSR_DCE1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_RI_DCE1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_DCD_DCE1, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
break;
case CSP_BASE_REG_PA_UART2:
DDKIomuxSetPinMux(DDK_IOMUX_PIN_TXD2, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_RXD2, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CTS2, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_RTS2, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_DTR_DCE2, DDK_IOMUX_OUT_FUNC,
DDK_IOMUX_IN_FUNC);
break;
case CSP_BASE_REG_PA_UART3:
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_MOSI, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_MISO, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_SPI_RDY, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_CSPI3_SCLK, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
break;
case CSP_BASE_REG_PA_UART4:
DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_CS0, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_CS1, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_DIOR, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_ATA_DIOW, DDK_IOMUX_OUT_ALT1,
DDK_IOMUX_IN_ALT1);
break;
case CSP_BASE_REG_PA_UART5:
DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_VS2, DDK_IOMUX_OUT_ALT2,
DDK_IOMUX_IN_ALT2);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_BVD1, DDK_IOMUX_OUT_ALT2,
DDK_IOMUX_IN_ALT2);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_BVD2, DDK_IOMUX_OUT_ALT2,
DDK_IOMUX_IN_ALT2);
DDKIomuxSetPinMux(DDK_IOMUX_PIN_PC_RST, DDK_IOMUX_OUT_ALT2,
DDK_IOMUX_IN_ALT2);
break;
default:
return result;
}
return TRUE;
}
//-----------------------------------------------------------------------------
//
// Function: BSPSerGetChannelPriority
//
// This function is a wrapper for Uart to find out the SDMA channel priority.
//
// Parameters:
//
// Returns:
// SDMA channel priority for Serial.
//
//-----------------------------------------------------------------------------
UINT8 BSPSerGetChannelPriority()
{
return BSP_SDMA_CHNPRI_SERIAL;
}
//-----------------------------------------------------------------------------
//
// Function: BSPSerGetDMAIsEnabled
//
// This function is a wrapper for Uart to find out if SDMA is to be used or not.
// The UARTs are identified based on the based address.
//
// Parameters:
// HWAddr
// [in] Physical IO address.
// Returns:
// TRUE if SDMA is to be used for this UART.
//
//-----------------------------------------------------------------------------
BOOL BSPSerGetDMAIsEnabled(ULONG HWAddr)
{
BOOL useDMA = FALSE;
switch (HWAddr) {
case CSP_BASE_REG_PA_UART1:
#if BSP_SDMA_SUPPORT_UART1
useDMA = TRUE;
#endif
break;
case CSP_BASE_REG_PA_UART2:
#if BSP_SDMA_SUPPORT_UART2
useDMA = TRUE;
#endif
break;
case CSP_BASE_REG_PA_UART3:
#if BSP_SDMA_SUPPORT_UART3
useDMA = TRUE;
#endif
break;
case CSP_BASE_REG_PA_UART4:
#if BSP_SDMA_SUPPORT_UART4
useDMA = TRUE;
#endif
break;
case CSP_BASE_REG_PA_UART5:
#if BSP_SDMA_SUPPORT_UART5
useDMA = TRUE;
#endif
break;
default:
break;
}
return useDMA;
}
//-----------------------------------------------------------------------------
//
// Function: BSPSerGetDMARequest
//
// This function is a wrapper for Uart to find out the TX/RX SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
// HWAddr
// [in] Physical IO address.
// reqRx
// [out] the RX SDMA request line to be used for this UART.
// reqTx
// [out] the TX SDMA request line to be used for this UART.
// Returns:
// TRUE if SDMA is to be used for this UART.
//
//-----------------------------------------------------------------------------
BOOL BSPSerGetDMARequest(ULONG HWAddr, int* reqRx, int* reqTx)
{
switch (HWAddr)
{
case CSP_BASE_REG_PA_UART1:
*reqRx = DDK_DMA_REQ_UART1_RX;
*reqTx = DDK_DMA_REQ_UART1_TX;
break;
case CSP_BASE_REG_PA_UART2:
*reqRx = DDK_DMA_REQ_UART2_RX;
*reqTx = DDK_DMA_REQ_UART2_TX;
break;
case CSP_BASE_REG_PA_UART3:
*reqRx = DDK_DMA_REQ_UART3_RX;
*reqTx = DDK_DMA_REQ_UART3_TX;
break;
case CSP_BASE_REG_PA_UART4:
*reqRx = DDK_DMA_REQ_UART4_RX;
*reqTx = DDK_DMA_REQ_UART4_TX;
break;
case CSP_BASE_REG_PA_UART5:
*reqRx = DDK_DMA_REQ_UART5_RX;
*reqTx = DDK_DMA_REQ_UART5_TX;
break;
default:
return FALSE;
}
return TRUE;
}
//-----------------------------------------------------------------------------
//
// Function: BSPSerSetDMAReqGpr
//
// This function is a wrapper for Uart to acquire a muxed SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
// HWAddr
// [in] Physical IO address.
// Returns:
// TRUE if success.
//
//-----------------------------------------------------------------------------
BOOL BSPSerAcquireDMAReqGpr(ULONG HWAddr)
{
BOOL bRet = FALSE;
// set the GPR bits to value that makes the corresponding UARTs work.
switch (HWAddr)
{
case CSP_BASE_REG_PA_UART2:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 0);
break;
case CSP_BASE_REG_PA_UART3:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI1_UART3, 1);
break;
case CSP_BASE_REG_PA_UART5:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI3_UART5, 1);
break;
default:
break;
}
return bRet;
}
//-----------------------------------------------------------------------------
//
// Function: BSPSerRestoreDMAReqGpr
//
// This function is a wrapper for Uart to restore a muxed SDMA request line.
// The UARTs are identified based on the based address.
//
// Parameters:
// HWAddr
// [in] Physical IO address.
// Returns:
// TRUE if success.
//
//-----------------------------------------------------------------------------
BOOL BSPSerRestoreDMAReqGpr(ULONG HWAddr)
{
BOOL bRet = TRUE;
// restore the GPR bits to power-on values.
switch (HWAddr)
{
case CSP_BASE_REG_PA_UART2:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_FIRI_UART2, 0);
break;
case CSP_BASE_REG_PA_UART3:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI1_UART3, 0);
break;
case CSP_BASE_REG_PA_UART5:
bRet = DDKIomuxSetGprBit(DDK_IOMUX_GPR_CSPI3_UART5, 0);
break;
default:
break;
}
return bRet;
}
//-----------------------------------------------------------------------------
//
// Function: BSPGetDMABuffSize
//
// This function is a wrapper for Uart to find out the TX/RX SDMA.
// The UARTs are identified based on the based address.
//
// Parameters:
// buffRx
// [out] the RX SDMA buffer size.
//
// buffTx
// [out] the RX SDMA buffer size
// Returns:
//
//
//-----------------------------------------------------------------------------
VOID BSPGetDMABuffSize(UINT16* buffRx, UINT16 * buffTx)
{
*buffRx = SERIAL_SDMA_RX_BUFFER_SIZE;
*buffTx = SERIAL_SDMA_TX_BUFFER_SIZE;
}
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