args.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//
//  Parameters:
//      pBSPArgs
//          [out] Points to BSP arguments structure to be updated.
//
//  Returns:
//      TRUE if boot successfully, otherwise returns FALSE.
//
//------------------------------------------------------------------------------
BOOL OALBspArgsInit(BSP_ARGS *pBSPArgs)
{
    UINT16 dsw;
    UINT32 pdr, ccmr, div, mcuPllFreq, ahbFreq;
    PCSP_PBC_REGS pPBC;
    PCSP_CCM_REGS pCCM;

    // Map access to PBC
    pPBC = (PCSP_PBC_REGS) OALPAtoUA(BSP_BASE_REG_PA_PBC_BASE);

    if (pPBC == NULL)
    {
        OALMSG(OAL_ERROR, (_T("ERROR: OALBspArgsInit: OALPAtoUA failed for PBC!\r\n")));
        return FALSE;
    }

    // Map access to CCM
    pCCM = (PCSP_CCM_REGS) OALPAtoUA(CSP_BASE_REG_PA_CCM);

    if (pCCM == NULL)
    {
        OALMSG(OAL_ERROR, (_T("ERROR: OALBspArgsInit: OALPAtoUA failed for CCM!\r\n")));
        return FALSE;
    }
    
    // Read board user switch setting
    dsw = INREG16(&pPBC->BSTAT2) & 0xFF;
    OALMSG(OAL_INFO, (TEXT("PBC debug switch settings:  0x%x\r\n"), dsw));

    // Initialize args structure with KITL configuration
    if (dsw & BSP_PBC_DSW_KITL)
    {
        pBSPArgs->kitl.flags |= OAL_KITL_FLAGS_PASSIVE;
        OALMSG(OAL_INFO, (TEXT("KITL will run in PASSIVE mode\r\n")));
    }

    // Initialize args structure with L2 configuration
    pBSPArgs->bL2enable = !(dsw & BSP_PBC_DSW_L2);

    // Check for alternate clocking override
    if (dsw & BSP_PBC_DSW_ALT_CLK)
    {
        mcuPllFreq = BSP_CLK_MCUPLL_FREQ_ALT;
    }

    // Else, use normal (non-TV) clocking
    else
    {
        mcuPllFreq = BSP_CLK_MCUPLL_FREQ;
    }

    // Determine if we will switch to high speed after PMIC supply
    // voltages have been configured.
    pBSPArgs->bHighSpeedEnable = !(dsw & BSP_PBC_DSW_ARM_CLK);
            
    // Initialize PLL clock configuration
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_MCUPLL] = mcuPllFreq;
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SERPLL] = BSP_CLK_SERPLL_FREQ;
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_USBPLL] = BSP_CLK_USBPLL_FREQ;
        
    // Get post dividers for MCU clock domain
    pdr = INREG32(&pCCM->PDR0);

    // Calculate MCU clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_MCU_PODF);    
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_ARM] = mcuPllFreq / (div + 1);
        
    // Calculate HSP (IPU) clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_HSP_PODF);
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_IPU] = mcuPllFreq / (div + 1);
    
    // Calculate AHB (MAX) clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_MAX_PODF);
    ahbFreq = mcuPllFreq / (div + 1);
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_AHB] = ahbFreq;

    // Calculate IPG clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_IPG_PODF);    
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_IPG] = ahbFreq / (div + 1);

    // Calculate NFC clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_NFC_PODF);    
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_NFC] = ahbFreq / (div + 1);
    
    // Calculate GACC clock frequency
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_GACC] = ahbFreq >> 1;

    // Calculate PER clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_PER_PODF);

    // PER clock source can be IPG_CLK or USBPLL and is selected by PERCS
    if (EXTREG32BF(&pCCM->CCMR, CCM_CCMR_PERCS) == CCM_CCMR_PERCS_USB_CLK)
    {
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_PER] = BSP_CLK_USBPLL_FREQ / (div + 1);
        
    }
    else
    {
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_PER] = 
            pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_IPG];
    }

    // Get clock source selections for peripheral clocks
    ccmr = INREG32(&pCCM->CCMR);     
    
    // Calculate SIM clock frequency (same as PERCLK)
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SIM] = 
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_PER];

    // Calculate CSI clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR0_CSI_PODF) + 1;
    switch (CSP_BITFEXT(ccmr, CCM_CCMR_CSCS))
    {
    case CCM_CCMR_CSCS_USB_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_CSI] = BSP_CLK_USBPLL_FREQ / div;
        break;

    case CCM_CCMR_CSCS_SERIAL_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_CSI] = BSP_CLK_SERPLL_FREQ / div;
        break;
    }

    // Get post dividers for peripheral baud clocks
    pdr = INREG32(&pCCM->PDR1);

    // Calculate SSI1 clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR1_SSI1_PRE_PODF) + 1;
    div *= (CSP_BITFEXT(pdr, CCM_PDR1_SSI1_PODF) + 1);
    switch (CSP_BITFEXT(ccmr, CCM_CCMR_SSI1S))
    {
    case CCM_CCMR_SSI1S_MCU_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI1] = mcuPllFreq / div;
        break;

    case CCM_CCMR_SSI1S_USB_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI1] = BSP_CLK_USBPLL_FREQ / div;
        break;

    case CCM_CCMR_SSI1S_SERIAL_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI1] = BSP_CLK_SERPLL_FREQ / div;
        break;
    }
        
    // Calculate SSI2 clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR1_SSI2_PRE_PODF) + 1;
    div *= (CSP_BITFEXT(pdr, CCM_PDR1_SSI2_PODF) + 1);
    switch (CSP_BITFEXT(ccmr, CCM_CCMR_SSI2S))
    {
    case CCM_CCMR_SSI2S_MCU_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI2] = mcuPllFreq / div;
        break;

    case CCM_CCMR_SSI2S_USB_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI2] = BSP_CLK_USBPLL_FREQ / div;
        break;

    case CCM_CCMR_SSI2S_SERIAL_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI2] = BSP_CLK_SERPLL_FREQ / div;
        break;
    }

    // Calculate FIRI clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR1_FIRI_PRE_PODF) + 1;
    div *= (CSP_BITFEXT(pdr, CCM_PDR1_FIRI_PODF) + 1);
    switch (CSP_BITFEXT(ccmr, CCM_CCMR_FIRS))
    {
    case CCM_CCMR_FIRS_MCU_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_FIRI] = mcuPllFreq / div;
        break;

    case CCM_CCMR_FIRS_USB_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_FIRI] = BSP_CLK_USBPLL_FREQ / div;
        break;

    case CCM_CCMR_FIRS_SERIAL_CLK:        
        pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_FIRI] = BSP_CLK_SERPLL_FREQ / div;
        break;
    }

    // Calculate USB clock frequency
    div = CSP_BITFEXT(pdr, CCM_PDR1_USB_PRDF) + 1;
    div *= (CSP_BITFEXT(pdr, CCM_PDR1_USB_PODF) + 1);
    pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_USB] = BSP_CLK_USBPLL_FREQ / div;

    OALMSG(OAL_INFO, (TEXT("BSP System Configuration:\r\n")));
    if (pBSPArgs->bL2enable)
    {
        OALMSG(OAL_INFO, (TEXT("    L2 CACHE ENABLED\r\n")));    
    }
    else
    {
        OALMSG(OAL_INFO, (TEXT("    L2 CACHE DISABLED\r\n")));    
    }
    OALMSG(OAL_INFO, (TEXT("    MCU PLL  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_MCUPLL]));    
    OALMSG(OAL_INFO, (TEXT("    USB PLL  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_USBPLL]));    
    OALMSG(OAL_INFO, (TEXT("    SER PLL  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SERPLL]));    
    OALMSG(OAL_INFO, (TEXT("    ARM CLOCK  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_ARM]));    
    OALMSG(OAL_INFO, (TEXT("    IPU CLOCK  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_IPU]));
    OALMSG(OAL_INFO, (TEXT("    AHB CLOCK  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_AHB]));
    OALMSG(OAL_INFO, (TEXT("    IPG CLOCK  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_IPG]));
    OALMSG(OAL_INFO, (TEXT("    NFC CLOCK  = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_NFC]));
    OALMSG(OAL_INFO, (TEXT("    GACC CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_GACC]));
    OALMSG(OAL_INFO, (TEXT("    PER CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_PER]));
    OALMSG(OAL_INFO, (TEXT("    SSI1 CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI1]));
    OALMSG(OAL_INFO, (TEXT("    SSI2 CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SSI2]));
    OALMSG(OAL_INFO, (TEXT("    FIRI CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_FIRI]));
    OALMSG(OAL_INFO, (TEXT("    CSI CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_CSI]));
    OALMSG(OAL_INFO, (TEXT("    USB CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_USB]));
    OALMSG(OAL_INFO, (TEXT("    SIM CLOCK = %d Hz\r\n"), pBSPArgs->clockFreq[DDK_CLOCK_SIGNAL_SIM]));

    // Reset the panic request count
    pBSPArgs->panicRequests = 0;
    
    return TRUE;
}


//------------------------------------------------------------------------------