k9k1g08u0b.h

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File:  K9K1G08U0B.h
//
//  Contains definitions for FMD impletation of the Samsung K9K1G08U0B NAND
//  flash memory device.
//
//------------------------------------------------------------------------------
#ifndef __K9K1G08U0B_H__
#define __K9K1G08U0B_H__

#define NAND_BLOCK_CNT          (8192)       // 8192 blocks
#define NAND_SECTOR_CNT         (32)         // Each Block has 32 Pages
#define NAND_SECTOR_SIZE        (512)        // Each Page has 512 Bytes
#define NAND_SECTORS_PERPAGE    (1)          // Each Page has 1 Sectors
#define NAND_SPARE_SIZE         (16)
#define NAND_BLOCK_SIZE         (NAND_SECTOR_CNT * NAND_SECTOR_SIZE)
#define NAND_BBI_OFFSET         5           // Bad block info spare offset
#define NAND_BUS_WIDTH          8           // 8-bit bus

#define NAND_MAKER_CODE         0xEC        // Samsung
#define NAND_DEVICE_CODE        0x79

#define NAND_STATUS_MASK_ERROR  (1U << 0)   // Status Bit0 indicates error

#define NAND_ID_CODE            ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)

// K9K1G08U0B address is sent in 4-cycles
//      1st Cycle:  Column address A[7:0]
//      2nd Cycle:  Page address A[16:9]
//      3rd Cycle:  Page address A[24:17]
//      4th Cycle:  Page address A[26:25]
#define NF_ADDR_COL(columnaddr)    { NF_ADDR((columnaddr) & 0xFF); }

#define NF_ADDR_PAGE(rowaddr)      { NF_ADDR((rowaddr) & 0xFF);         \
                                     NF_ADDR(((rowaddr) >> 8) & 0xFF);  \
                                     NF_ADDR(((rowaddr) >> 16) & 0x3); }     

// K9K1G08U0B supports sequential row and serial page access, so we only
// need to send read command and address on first access.
#define NF_READ_SEQ(sectAddr)   (TRUE)

#endif    // __K9K1G08U0B_H__