k9f1g08u0a.h

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
//  File:  K9F1G08U0A.h
//
//  Contains definitions for FMD impletation of the Samsung K9F1G08U0A NAND
//  flash memory device.
//
//------------------------------------------------------------------------------
#ifndef __K9F1G08U0A_H__
#define __K9F1G08U0A_H__

#define NAND_LARGE_PAGE

#define NAND_BLOCK_CNT          (1024)       // 1024 blocks

// In fact, each block of K9F1G08U0A consists of 64 pages and the page size 
// is 2k bytes. We simulate it as a small page size nand flash, so the sector
// size is still 512 bytes and each block has 64 * (2048 / 512) = 256 sectors.
// The simulation is necessary for Microsoft up layer(fal, mspart, file 
// system) does not support the 2k page size nand flash directly.
#define NAND_SECTOR_CNT         (256)        // Each Block has 32 Sectors
#define NAND_SECTOR_SIZE        (512)        // Each Sector has 512 Bytes
#define NAND_SECTORS_PERPAGE    (4)          // Each Page has 4 Sectors
#define NAND_SPARE_SIZE         (16)
#define NAND_BLOCK_SIZE         (NAND_SECTOR_CNT * NAND_SECTOR_SIZE)
#define NAND_BBI_OFFSET         5           // Bad block info spare offset
#define NAND_BUS_WIDTH          8           // 8-bit bus

#define NAND_MAKER_CODE         0xEC        // Samsung
#define NAND_DEVICE_CODE        0xF1

#define NAND_STATUS_MASK_ERROR  (1U << 0)   // Status Bit0 indicates error

#define NAND_ID_CODE            ((NAND_DEVICE_CODE << 8) | NAND_MAKER_CODE)


// K9F1G08U0A address is sent in 4-cycles
//      1st Cycle:  Column address A[7:0]
//      2nd Cycle:  Column address A[11:8]
//      3rd Cycle:  Page address A[19:12]
//      4th Cycle:  Page address A[27:20]
#define NF_ADDR_COL(columnaddr)       { NF_ADDR((columnaddr) & 0xFF);   \
                                        NF_ADDR(((columnaddr) >>  8) & 0xF); }

#define NF_ADDR_PAGE(rowaddr)         { NF_ADDR((rowaddr) & 0xFF);      \
                                        NF_ADDR(((rowaddr) >> 8) & 0xFF); }    

// sequential read operation is not supported by K9F1G08U0A
#define NF_READ_SEQ(sectAddr)   (FALSE)

#endif    // __K9F1G08U0A_H__