timer.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//-----------------------------------------------------------------------------
//
//  Module: timer.c
//
//  This module provides the BSP-specific interfaces required to support
//  the PQOAL timer code.
//
//-----------------------------------------------------------------------------
#include <bsp.h>

extern void OALCPUEnterWFI(void);
extern PCSP_AVIC_REGS g_pAVIC;
extern PCSP_PBC_REGS g_pPBC;
extern UINT32 g_SREV;

//-----------------------------------------------------------------------------
//
//  Function: OALTimerGetClkSrc
//
//  This function returns the clock source setting used to program the EPIT_CR
//  CLKSRC bits.
//
//  Parameters:
//      None.
//
//  Returns:
//      EPIT clock source selection.
//
//-----------------------------------------------------------------------------
UINT32 OALTimerGetClkSrc(void)
{
#ifdef VPMX31
    return EPIT_CR_CLKSRC_CKIL;
#else
    return EPIT_CR_CLKSRC_CKIH;
#endif
}


//-----------------------------------------------------------------------------
//
//  Function: OALTimerGetClkPrescalar
//
//  This function returns the clock prescalar used to program the EPIT_CR
//  PRESCALER bits.
//
//  Parameters:
//      None.
//
//  Returns:
//      EPIT prescalar.
//
//-----------------------------------------------------------------------------
UINT32 OALTimerGetClkPrescalar(void)
{
#ifdef VPMX31
    return 0;
#else
    return BSP_EPIT_PRESCALAR;
#endif
}


//-----------------------------------------------------------------------------
//
//  Function: OALTimerGetClkFreq
//
//  This function returns the frequency of the EPIT input clock.
//
//  Parameters:
//      None.
//
//  Returns:
//      EPIT input clock.
//
//-----------------------------------------------------------------------------
UINT32 OALTimerGetClkFreq(void)
{
#ifdef VPMX31
    return BSP_CLK_CKIL_FREQ;
#else
    BSP_ARGS *pBspArgs = (BSP_ARGS *)IMAGE_SHARE_ARGS_UA_START;

    return pBspArgs->clockFreq[DDK_CLOCK_SIGNAL_PER];
#endif
}


//-----------------------------------------------------------------------------
//
//  Function: OALCPUIdle
//
//  This function puts the CPU or SOC in idle state. The CPU or SOC 
//  should exit the idle state when an interrupt occurs. This function is 
//  called with interrupts are disabled. When this function returns, interrupts 
//  must be disabled also.
//
//  Parameters:
//      None.
//
//  Returns:
//      None.
//
//-----------------------------------------------------------------------------
VOID OALCPUIdle()
{        
#ifdef BSP_FAKE_IDLE
    // Wait until AVIC reports an interrupt is pending
    while((!INREG32(&g_pAVIC->NIPNDH)) && (!INREG32(&g_pAVIC->NIPNDL)));
#else

    // Check silicon rev and avoid WFI on rev 1.0 silicon
    if (g_SREV == 0)
    {
        // Wait until AVIC reports an interrupt is pending
        while((!INREG32(&g_pAVIC->NIPNDH)) && (!INREG32(&g_pAVIC->NIPNDL)));
    }

    else
    {
        //OUTREG16(&g_pPBC->BCTRL1_SET, CSP_BITFMASK(PBC_BCTRL1_SET_LED0));

        // Enter wait-for-interrupt mode
        OALCPUEnterWFI();

        //OUTREG16(&g_pPBC->BCTRL1_CLEAR, CSP_BITFMASK(PBC_BCTRL1_CLEAR_LED0));
    }
#endif
    
}


//-----------------------------------------------------------------------------
//
//  Function: OALWdogGetConfig
//
//  This function provides the watchdog timer configuration.
//
//  Parameters:
//      None.
//
//  Returns:
//      Watchdog configuration.
//
//-----------------------------------------------------------------------------
UINT16 OALWdogGetConfig()
{
    // Upper layers will configure watchdog timeout (WT field) and enable
    // the watchdog (WE) field.  Other bits in WCR are configured as follows:
    //
    //  WDW = continue timer operation in low-power wait mode
    //  WOE = tri-state WDOG output pin
    //  WDA = no software assertion of WDOG output pin
    //  SRS = no software reset of WDOG
    //  WRE = generate reset signal upon watchdog timeout
    //  WDE = disable watchdog (will be enabled after configuration)
    //  WDBG = suspend timer operation in debug mode
    //  WDZST = suspend timer operation in low-power stop mode
    return  CSP_BITFVAL(WDOG_WCR_WOE, WDOG_WCR_WOE_TRISTATE) |
            CSP_BITFVAL(WDOG_WCR_WDA, WDOG_WCR_WDA_NOEFFECT) |
            CSP_BITFVAL(WDOG_WCR_SRS, WDOG_WCR_SRS_NOEFFECT) |
            CSP_BITFVAL(WDOG_WCR_WRE, WDOG_WCR_WRE_SIG_RESET) |
            CSP_BITFVAL(WDOG_WCR_WDE, WDOG_WCR_WDE_DISABLE) |
            CSP_BITFVAL(WDOG_WCR_WDBG, WDOG_WCR_WDBG_SUSPEND) |
            CSP_BITFVAL(WDOG_WCR_WDZST, WDOG_WCR_WDZST_SUSPEND);
}