📄 startup.s
字号:
; ------------
; 0xFF831A39
ldr r0, =0xFF831A39
str r0, [r1, #CCM_PDR0_OFFSET]
CLK_MCUPLL_532_FPM
; MCU PLL control (MPCTL)
;
; MCU_CLK = (FPM) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (32768 KHz * 1024) * 2 * (7 + 460/(495+1)) / (0+1)
; = 532 MHz
;
; MFN = 460 = (460 << 0) = 0x000001CC
; MFI = 7 = (7 << 10) = 0x00001C00
; MFD = 495 = (495 << 16) = 0x01EF0000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x01EF1DCC
ldr r0, =0x01EF1DCC
str r0, [r1, #CCM_MPCTL_OFFSET]
b WEIM_CONFIG
;
; PLL reference is CKIH
;
CKIH_PLL_REF
; Control register (CCMR):
;
; FPME = FPM disabled = (1 << 0) = 0x00000000
; PRCS = CKIH is PLL ref = (2 << 1) = 0x00000004
; MPE = MCU PLL enabled = (1 << 3) = 0x00000008
; SBYCS = Enabled in standby = (1 << 4) = 0x00000010
; ROMW = All masters 1 WS = (3 << 5) = 0x00000060
; MDS = MCU PLL is source = (0 << 7) = 0x00000000
; SPE = serial PLL enabled = (1 << 8) = 0x00000100
; UPE = USB PLL enabled = (1 << 9) = 0x00000200
; WAMO = masked all but DSM = (0 << 10) = 0x00000000
; FIRS = FIRI source usb_clk = (1 << 11) = 0x00000800
; LPM = wait mode = (0 << 14) = 0x00000000
; RAMW = All masters 1 WS = (3 << 16) = 0x00030000
; SSI1S = SSI1 source serial_clk = (2 << 18) = 0x00080000
; SSI1S = SSI2 source serial_clk = (2 << 21) = 0x00400000
; PERCS = per_clk source ipg_clk = (1 << 24) = 0x01000000
; CSCS = CSI source SRPLL = (1 << 25) = 0x02000000
; FPMF = FPM factor 1024 = (1 << 26) = 0x04000000
; WBEN = well bias disabled = (0 << 27) = 0x00000000
; VSTBY = no standby = (0 << 28) = 0x00000000
; L2PG = no L2 power gating (0 << 29) = 0x00000000
; ------------
; 0x074B0B7C
ldr r0, =0x074B0B7C
str r0, [r1, #CCM_CCMR_OFFSET]
; Check for forced alternate clocking
ands r0, r5, #BSP_PBC_DSW_ALT_CLK
bne CLK_ALT
; Configure the Serial PLL
;
; SERPLL = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (26 MHz) * 2 * (8 + 292/(624+1)) / (1+1)
; = 220.1472 MHz
;
; MFN = 292 = (292 << 0) = 0x00000124
; MFI = 8 = (8 << 10) = 0x00002000
; MFD = 624 = (624 << 16) = 0x02700000
; PD = 1 = (1 << 26) = 0x04000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x06702124
ldr r0, =0x06702124
str r0, [r1, #CCM_SPCTL_OFFSET]
; Configure the USB PLL
;
; USBPLL = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (26 MHz) * 2 * (9 + 12/(51+1)) / (1+1)
; = 240 MHz
;
; MFN = 12 = (12 << 0) = 0x0000000C
; MFI = 9 = (9 << 10) = 0x00002400
; MFD = 51 = (51 << 16) = 0x00330000
; PD = 1 = (1 << 26) = 0x04000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x0433240C
ldr r0, =0x0433240C
str r0, [r1, #CCM_UPCTL_OFFSET]
; Determine AHB clock configuration
and r0, r5, #BSP_PBC_DSW_AHB_CLK
cmp r0, #BSP_PBC_DSW_AHB_66
beq CLK_AHB_66
; Fall though to CLK_AHB_133
CLK_AHB_133
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 532 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 266 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 133 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 4 = 133 MHz
; IPG_CLK = HCLK / 2 = 66.5 MHz
; NFC_CLK = HCLK / 5 = 26.6 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /1 = (1 << 0) = 0x00000001
; MAX_PODF = /4 = (3 << 3) = 0x00000018
; IPG_PODF = /2 = (1 << 6) = 0x00000040
; NFC_PODF = /5 = (4 << 8) = 0x00000400
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831C59
ldr r0, =0xFF831C59
str r0, [r1, #CCM_PDR0_OFFSET]
b CLK_MCUPLL_532
CLK_AHB_66
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 532 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 266 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 133 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 8 = 66.5 MHz
; IPG_CLK = HCLK / 1 = 66.5 MHz
; NFC_CLK = HCLK / 3 = 22.167 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /2 = (1 << 0) = 0x00000001
; MAX_PODF = /8 = (7 << 3) = 0x00000038
; IPG_PODF = /1 = (0 << 6) = 0x00000000
; NFC_PODF = /3 = (2 << 8) = 0x00000200
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831A39
ldr r0, =0xFF831A39
str r0, [r1, #CCM_PDR0_OFFSET]
CLK_MCUPLL_532
; MCU PLL control (MPCTL)
;
; MCU_CLK = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (26 MHz) * 2 * (10 + 12/(51+1)) / (0+1)
; = 532 MHz
;
; MFN = 12 = (12 << 0) = 0x0000000C
; MFI = 10 = (10 << 10) = 0x00002800
; MFD = 51 = (51 << 16) = 0x00330000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x0033280C
ldr r0, =0x0033280C
str r0, [r1, #CCM_MPCTL_OFFSET]
b WEIM_CONFIG
CLK_ALT
; Configure the Serial PLL
;
; SERPLL = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (27 MHz) * 2 * (8 + 96/(624+1)) / (1+1)
; = 220.1472 MHz
;
; MFN = 96 = (96 << 0) = 0x00000060
; MFI = 8 = (8 << 10) = 0x00002000
; MFD = 624 = (624 << 16) = 0x02700000
; PD = 1 = (1 << 26) = 0x04000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x06702060
ldr r0, =0x06702060
str r0, [r1, #CCM_SPCTL_OFFSET]
; Configure the USB PLL
;
; USBPLL = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (27 MHz) * 2 * (8 + 48/(53+1)) / (1+1)
; = 240 MHz
;
; MFN = 48 = (48 << 0) = 0x00000030
; MFI = 8 = (8 << 10) = 0x00002000
; MFD = 53 = (53 << 16) = 0x00350000
; PD = 1 = (1 << 26) = 0x04000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x04352030
ldr r0, =0x04352030
str r0, [r1, #CCM_UPCTL_OFFSET]
; Post-divider Register 0 (PDR0):
;
; MCU_MAIN_CLK = 528 MHz (see MPCLT programming below)
;
; MCU_CLK = MCU_MAIN_CLK / 2 = 264 MHz
; HSP_CLK = MCU_MAIN_CLK / 4 = 132 MHz
; MAX_CLK = HCLK = MCU_MAIN_CLK / 4 = 132 MHz
; IPG_CLK = HCLK / 2 = 66 MHz
; NFC_CLK = HCLK / 5 = 26.4 MHz
; PER_CLK = USB_CLK / 4
; CSI_CLK = USB_CLK / 512
;
; MCU_PODF = /2 = (1 << 0) = 0x00000001
; MAX_PODF = /4 = (3 << 3) = 0x00000018
; IPG_PODF = /2 = (1 << 6) = 0x00000040
; NFC_PODF = /5 = (4 << 8) = 0x00000400
; HSP_PODF = /4 = (3 << 11) = 0x00001800
; PER_PODF = /4 = (3 << 16) = 0x00030000
; CSI_PODF = /512 = (511 << 23) = 0xFF800000
; ------------
; 0xFF831C59
ldr r0, =0xFF831C59
str r0, [r1, #CCM_PDR0_OFFSET]
CLK_MCUPLL_ALT
; MCU PLL control (MPCTL)
;
; MCU_CLK = (CKIH) * 2 * (MFI + MFN/(MFD+1)) / (PDF+1)
; = (27 MHz) * 2 * (9 + 42/(53+1)) / (0+1)
; = 528 MHz
;
; MFN = 42 = (42 << 0) = 0x0000002A
; MFI = 9 = (9 << 10) = 0x00002400
; MFD = 53 = (53 << 16) = 0x00350000
; PD = 0 = (0 << 26) = 0x00000000
; BRMO = first order = (0 << 31) = 0x00000000
; ------------
; 0x0035242A
ldr r0, =0x0035242A
str r0, [r1, #CCM_MPCTL_OFFSET]
WEIM_CONFIG
;
; Configure wireless external interface module (WEIM)
;
;
; Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
;
ldr r1, =CSP_BASE_MEM_PA_CS0
ldr r0, =0xF0F0
strh r0, [r1]
; 1st command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xAAAA
strh r0, [r2]
; 2nd command
ldr r2, =0x554
add r2, r2, r1
ldr r0, =0x5555
strh r0, [r2]
; 3rd command
ldr r2, =0xAAA
add r2, r2, r1
ldr r0, =0xD0D0
strh r0, [r2]
; Write flash config register
ldr r0, =0x56CA
strh r0, [r2]
; Flash reset command
ldr r0, =0xF0F0
strh r0, [r1]
ldr r1, =CSP_BASE_REG_PA_WEIM
; CS0 control (upper)
; EDC - 3 extra dead cycles (3 << 0) = 0x00000003
; WWS - 0 extra write wait states (0 << 4) = 0x00000000
; EW - Posedge DTACK (0 << 7) = 0x00000000
; WSC - 12 wait states (12 << 8) = 0x00000C00
; CNC - 3 CS negation cycles (3 << 14) = 0x0000C000
; DOL - 0 clock burst latency (0 << 16) = 0x00000000
; SYNC - Disable sync burst (0 << 20) = 0x00000000
; PME - Disable page mode (0 << 21) = 0x00000000
; PSZ - 4 word burst/page (0 << 22) = 0x00000000
; BCS - 1 BCLK delay (0 << 24) = 0x00000000
; BCD - /1 burst clock (0 << 28) = 0x00000000
; WP - No write protect (0 << 30) = 0x00000000
; SP - All user mode access (0 << 31) = 0x00000000
; ------------
; 0x0000CC03
;ldr r0, =0x0000CC03
ldr r0, =0x23524E80
str r0, [r1, #WEIM_CSCR0U_OFFSET]
; CS0 control (lower)
; CSEN - Enable chip select (1 << 0) = 0x00000001
; WRAP - No wrap (0 << 1) = 0x00000000
; CRE - CRE pin 0 (0 << 2) = 0x00000000
; PSR - PSRAM mode disabled (0 << 3) = 0x00000000
; CSN - 2 AHB clocks (2 << 4) = 0x00000000
; DSZ - 16-bit DATA[15:0] (5 << 8) = 0x00000500
; EBC - Only write asserts EB (1 << 11) = 0x00000800
; CSA - 2 half AHB clocks (0 << 12) = 0x00000000
; EBWN - 3 half AHB clocks (3 << 16) = 0x00030000
; EBWA - 3 half AHB clocks (3 << 20) = 0x00300000
; OEN - 2 half AHB clocks (0 << 24) = 0x00000000
; OEA - 10 half AHB clocks (10 << 28) = 0xA0000000
; ------------
; 0xA0330D01
;ldr r0, =0xA0330D01
ldr r0, =0x10000D03
str r0, [r1, #WEIM_CSCR0L_OFFSET]
; CS0 control (additional)
; FCE - Data capture by AHB clk (0 << 0) = 0x00000000
; CNC2 - No CNC increase (0 << 1) = 0x00000000
; AGE - Disable ack glue logic (0 << 2) = 0x00000000
; WWU - Forbit wrap on write (0 << 3) = 0x00000000
; DCT - 2 AHB clocks (0 << 4) = 0x00000000
; DWW - wait states same as read (0 << 6) = 0x00000000
; LBA - 0 half AHB clock (0 << 8) = 0x00000000
; LBN - 2 half AHB clocks (2 << 10) = 0x00000800
; LAH - 3 half AHB clocks (2 << 13) = 0x00000000
; MUM - Non-muxed mode (0 << 14) = 0x00000000
; RWN - 2 half AHB clocks (2 << 16) = 0x00020000
; RWA - 2 half AHB clocks (2 << 20) = 0x00200000
; EBRN - 0 half AHB clocks (0 << 24) = 0x00000000
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