startup.s

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

;******************************************************************************
;*
;* Copyright (c) Microsoft Corporation.  All rights reserved.
;*
;* Use of this source code is subject to the terms of the Microsoft end-user
;* license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
;* If you did not accept the terms of the EULA, you are not authorized to use
;* this source code. For a copy of the EULA, please see the LICENSE.RTF on your
;* install media.
;*
;******************************************************************************
;*
;* Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
;* THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
;* AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
;*
;******************************************************************************
;*
;* FILE:    startup.s
;*
;* PURPOSE: Before control is transferred to the kernel, the boot loader
;*          calls this StartUp code to put the CPU into an initialized state.
;*
;******************************************************************************

;!!!!! TODO:  move constants to include file

    INCLUDE mxarm11_base_regs.inc
    INCLUDE mxarm11_base_mem.inc
    INCLUDE mx31_base_regs.inc
    INCLUDE mx31_base_mem.inc

;
; ARM constants
;
ARM_CPSR_PRECISE            EQU     (1 << 8)
ARM_CPSR_IRQDISABLE         EQU     (1 << 7)
ARM_CPSR_FIQDISABLE         EQU     (1 << 6)
ARM_CPSR_MODE_SVC           EQU     0x13
ARM_CTRL_ICACHE             EQU     (1 << 12)
ARM_CTRL_DCACHE             EQU     (1 << 2)
ARM_CTRL_MMU                EQU     (1 << 0)
ARM_CTRL_FLOW               EQU     (1 << 11)
ARM_CTRL_VECTORS            EQU     (1 << 13)
ARM_CTRL_FI                 EQU     (1 << 21)
ARM_CTRL_U                  EQU     (1 << 22)
ARM_CACR_FULL               EQU     0x3
ARM_AUXCR_SB                EQU     (1 << 2)
ARM_AUXCR_DB                EQU     (1 << 1)
ARM_AUXCR_HUM               EQU     (1 << 31)

; VFP uses coproc 10 for single-precision instructions
ARM_VFP_SP_COP              EQU     10
ARM_VFP_SP_ACCESS           EQU     (ARM_CACR_FULL << (ARM_VFP_SP_COP*2))

; VFP uses coproc 11 for double-precision instructions
ARM_VFP_DP_COP              EQU     11
ARM_VFP_DP_ACCESS           EQU     (ARM_CACR_FULL << (ARM_VFP_DP_COP*2))

; Configure coprocessor access control
ARM_CACR_CONFIG             EQU     (ARM_VFP_SP_ACCESS | ARM_VFP_DP_ACCESS)

; Peripheral Port Memory Remap Register (PPMRR)
ARM_PPMRR_SIZE_LSH          EQU     0
ARM_PPMRR_SIZE_WID          EQU     5
ARM_PPMRR_SIZE_256MB        EQU     0x13
ARM_PPMRR_SIZE_512MB        EQU     0x14
ARM_PPMRR_SIZE_1GB          EQU     0x15
ARM_PPMRR_BASEADDR_LSH      EQU     12
ARM_PPMRR_BASEADDR_WID      EQU     20

ARM_PPMRR_SIZE              EQU     (ARM_PPMRR_SIZE_1GB << ARM_PPMRR_SIZE_LSH)
ARM_PPMRR_BASEADDR          EQU     (CSP_BASE_MEM_PA_AIPSA)

ARM_PPMRR_CONFIG            EQU     (ARM_PPMRR_BASEADDR | ARM_PPMRR_SIZE)

;
; L2CC constants
;
L2CC_CR_OFFSET              EQU     0x100
L2CC_AUXCR_OFFSET           EQU     0x104
L2CC_INVWAY_OFFSET          EQU     0x77C
L2CC_DBGCR_OFFSET           EQU     0xF40

;
; AVIC constants
;
AVIC_INTCNTL_OFFSET         EQU     0x0000
AVIC_NIMASK_OFFSET          EQU     0x0004
AVIC_INTENNUM_OFFSET        EQU     0x0008
AVIC_INTDISNUM_OFFSET       EQU     0x000C
AVIC_INTENABLEH_OFFSET      EQU     0x0010
AVIC_INTENABLEL_OFFSET      EQU     0x0014
AVIC_INTTYPEH_OFFSET        EQU     0x0018
AVIC_INTTYPEL_OFFSET        EQU     0x001C
AVIC_NIPRIORITY7_OFFSET     EQU     0x0020
AVIC_NIPRIORITY6_OFFSET     EQU     0x0024
AVIC_NIPRIORITY5_OFFSET     EQU     0x0028
AVIC_NIPRIORITY4_OFFSET     EQU     0x002C
AVIC_NIPRIORITY3_OFFSET     EQU     0x0030
AVIC_NIPRIORITY2_OFFSET     EQU     0x0034
AVIC_NIPRIORITY1_OFFSET     EQU     0x0038
AVIC_NIPRIORITY0_OFFSET     EQU     0x003C
AVIC_NIVECSR_OFFSET         EQU     0x0040
AVIC_FIVECSR_OFFSET         EQU     0x0044
AVIC_INTSRCH_OFFSET         EQU     0x0048
AVIC_INTSRCL_OFFSET         EQU     0x004C
AVIC_INTFRCH_OFFSET         EQU     0x0050
AVIC_INTFRCL_OFFSET         EQU     0x0054
AVIC_NIPNDH_OFFSET          EQU     0x0058
AVIC_NIPNDL_OFFSET          EQU     0x005C
AVIC_FIPNDH_OFFSET          EQU     0x0060
AVIC_FIPNDL_OFFSET          EQU     0x0064
AVIC_VECTOR_OFFSET          EQU     0x0100

AVIC_INTCNTL_ABFFLAG        EQU     (1<<25)
AVIC_INTCNTL_ABFEN          EQU     (1<<24)
AVIC_INTCNTL_NIDIS          EQU     (1<<22)
AVIC_INTCNTL_FIDIS          EQU     (1<<21)
AVIC_INTCNTL_NIAD           EQU     (1<<20)
AVIC_INTCNTL_FIAD           EQU     (1<<19)
AVIC_INTCNTL_NM             EQU     (1<<18)


;
; RTC Constants
;
RTC_HOUR_MIN_COUNTER       EQU     0x0000
RTC_SEC_COUNTER            EQU     0x0004
RTC_HOUR_MIN_ALARM         EQU     0x0008
RTC_SEC_ALARM              EQU     0x000C
RTC_CONTROL                EQU     0x0010
RTC_INT_STAT               EQU     0x0014
RTC_INT_ENABLE             EQU     0x0018
RTC_STOPWATCH              EQU     0x001C
RTC_DAY_COUNTER            EQU     0x0020
RTC_DAY_ALARM              EQU     0x0024

;
; AIPS Constants
;
AIPSREG_MPR0_OFFSET         EQU     0x0000
AIPSREG_MPR1_OFFSET         EQU     0x0004
AIPSREG_PACR0_OFFSET        EQU     0x0020
AIPSREG_PACR1_OFFSET        EQU     0x0024
AIPSREG_PACR2_OFFSET        EQU     0x0028
AIPSREG_PACR3_OFFSET        EQU     0x002C
AIPSREG_OPACR0_OFFSET       EQU     0x0040
AIPSREG_OPACR1_OFFSET       EQU     0x0044
AIPSREG_OPACR2_OFFSET       EQU     0x0048
AIPSREG_OPACR3_OFFSET       EQU     0x004C
AIPSREG_OPACR4_OFFSET       EQU     0x0050

;
; MAX Constants
;
MAX_MPR0_OFFSET             EQU     0x0000
MAX_SGPCR0_OFFSET           EQU     0x0010
MAX_MPR1_OFFSET             EQU     0x0100
MAX_SGPCR1_OFFSET           EQU     0x0110
MAX_MPR2_OFFSET             EQU     0x0200
MAX_SGPCR2_OFFSET           EQU     0x0210
MAX_MPR3_OFFSET             EQU     0x0300
MAX_SGPCR3_OFFSET           EQU     0x0310
MAX_MPR4_OFFSET             EQU     0x0400
MAX_SGPCR4_OFFSET           EQU     0x0410
MAX_MGPCR0_OFFSET           EQU     0x0800
MAX_MGPCR1_OFFSET           EQU     0x0900
MAX_MGPCR2_OFFSET           EQU     0x0A00
MAX_MGPCR3_OFFSET           EQU     0x0B00
MAX_MGPCR4_OFFSET           EQU     0x0C00
MAX_MGPCR5_OFFSET           EQU     0x0D00


;
; M3IF Constants
;
M3IF_M3IFCTL_OFFSET         EQU     0x0000

;
; SPBA Constants
;
SPBA_PRR_OFFSET             EQU     0x0000

SPBA_PRR_RAR_ARM_ACCESS     EQU     (1 << 0)
SPBA_PRR_RAR_DSP_ACCESS     EQU     (1 << 1)
SPBA_PRR_RAR_DMA_ACCESS     EQU     (1 << 2)

SPBA_PRR_ROI_UNOWNED        EQU     (0 << 16)
SPBA_PRR_ROI_ARM_OWNED      EQU     (1 << 16)
SPBA_PRR_ROI_DSP_OWNED      EQU     (2 << 16)
SPBA_PRR_ROI_DMA_OWNED      EQU     (3 << 16)

SPBA_PRR_RMO_UNOWNED        EQU     (0 << 30)
SPBA_PRR_RMO_ALT_OWNED      EQU     (2 << 30)
SPBA_PRR_RMO_REQ_OWNED      EQU     (3 << 30)

SPBA_NUM_SHARED_PERIPH      EQU     (14)

;
; CCM constants
;
CCM_CCMR_OFFSET             EQU     0x0000
CCM_PDR0_OFFSET             EQU     0x0004
CCM_RCSR_OFFSET             EQU     0x000C
CCM_MPCTL_OFFSET            EQU     0x0010
CCM_UPCTL_OFFSET            EQU     0x0014
CCM_SPCTL_OFFSET            EQU     0x0018

;
; WEIM constants
;
WEIM_CSCR0U_OFFSET          EQU     0x0000
WEIM_CSCR4U_OFFSET          EQU     0x0040
WEIM_CSCR0L_OFFSET          EQU     0x0004
WEIM_CSCR4L_OFFSET          EQU     0x0044
WEIM_CSCR0A_OFFSET          EQU     0x0008
WEIM_CSCR4A_OFFSET          EQU     0x0048

;
; ESDCTL constants
;
ESDCTL_ESDCTL0_OFFSET       EQU     0x0000
ESDCTL_ESDCFG0_OFFSET       EQU     0x0004
ESDCTL_ESDCTL1_OFFSET       EQU     0x0008
ESDCTL_ESDCFG1_OFFSET       EQU     0x000C
ESDCTL_ESDMISC_OFFSET       EQU     0x0010
ESDCTL_ESDDLY5_OFFSET       EQU     0x0030

;
; PBC constants
;
PBC_BSTAT2_OFFSET           EQU     0x0002
PBC_BCTRL1_SET_OFFSET       EQU     0x0004
PBC_BCTRL1_CLR_OFFSET       EQU     0x0006
BSP_PBC_DSW_KITL            EQU     (1 << 0)    ; SW3_8:  ON = ACTIVE, OFF = PASSIVE
BSP_PBC_DSW_L2              EQU     (1 << 1)    ; SW3_7:  ON = L2 enabled, OFF = L2 disabled
BSP_PBC_DSW_AHB_CLK         EQU     (1 << 2)    ; SW3_6:  ON = 133MHz, OFF = 66MHz
BSP_PBC_DSW_ARM_CLK         EQU     (1 << 3)    ; SW3_5:  ON = 532MHz, OFF = 266MHz
BSP_PBC_DSW_ALT_CLK         EQU     (1 << 4)    ; SW3_4:  ON = SW3[5:6] determine clocking
                                                ;         OFF = Force alternalte clocking
BSP_PBC_DSW_L2_WT           EQU     (1 << 7)    ; SW3_1   ON = L2 write-through, OFF = L2 write-back
BSP_PBC_DSW_CLK_MSK         EQU     (BSP_PBC_DSW_AHB_CLK | BSP_PBC_DSW_ARM_CLK)
BSP_PBC_DSW_AHB_133         EQU     (0 << 2)
BSP_PBC_DSW_AHB_66          EQU     (1 << 2)
BSP_PBC_DSW_CLK_532_133     EQU     (0 << 2)
BSP_PBC_DSW_CLK_532_66      EQU     (1 << 2)
BSP_PBC_DSW_CLK_266_133     EQU     (2 << 2)
BSP_PBC_DSW_CLK_266_66      EQU     (3 << 2)



    IF :LNOT: :DEF: BOOTLOADER
        GBLL        BOOTLOADER
BOOTLOADER      SETL    {FALSE}
    ENDIF

    OPT 2                                       ; disable listing
    INCLUDE kxarm.h
    OPT 1                                       ; reenable listing
   

    IF :LNOT: BOOTLOADER
        IMPORT  KernelStart
    ENDIF
   
    IMPORT  OALClearUTLB


;******************************************************************************
;*
;* FUNCTION:    StartUp
;*
;* DESCRIPTION: System bootstrap function
;*
;* PARAMETERS:  None
;*
;* RETURNS:     None
;*
;******************************************************************************
 
    STARTUPTEXT
    LEAF_ENTRY StartUp

    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Put the processor in supervisor mode
    ; Disable the interrupt request (IRQ) and fast interrupt request (FIQ) 
    ; inputs
    ;--------------------------------------------------------------------------
    mrs     r0, cpsr                            ; r0 = CPSR
    mov     r0, #ARM_CPSR_MODE_SVC              ; enter supervisor mode
    orr     r0, r0, #ARM_CPSR_IRQDISABLE        ; disable normal IRQ
    orr     r0, r0, #ARM_CPSR_FIQDISABLE        ; disable fast IRQ
    ;orr     r0, r0, #ARM_CPSR_PRECISE           ; enable precise data aborts
    msr     cpsr_xc, r0                         ; update CPSR control bits

    ;
    ; Configure auxiliary control register 
    ;
    mrc     p15, 0, r0, c1, c0, 1               ; r0 = auxiliary control reg
    ;bic     r0, r0, #ARM_AUXCR_DB              ; disable dynamic branch pred
    ;bic     r0, r0, #ARM_AUXCR_SB              ; disable static branch pred
    orr     r0, r0, #ARM_AUXCR_HUM              ; disable hit under miss (Errata 364296)
    mcr     p15, 0, r0, c1, c0, 1               ; update auxiliary control reg
    
    ;--------------------------------------------------------------------------
    ; MS RECOMMENDATION:
    ; Disable memory management unit (MMU) and both the instruction and data 
    ; caches
    ;--------------------------------------------------------------------------
    mrc     p15, 0, r0, c1, c0, 0               ; r0 = system control reg
    bic     r0, r0, #ARM_CTRL_ICACHE            ; disable ICache
    bic     r0, r0, #ARM_CTRL_DCACHE            ; disable DCache
    bic     r0, r0, #ARM_CTRL_MMU               ; disable MMU
    bic     r0, r0, #ARM_CTRL_VECTORS           ; set vector base to 0x00000000
    orr     r0, r0, #ARM_CTRL_FLOW              ; program flow predicition enabled
    orr     r0, r0, #ARM_CTRL_FI                ; enable low interrupt latency (Errata 364296)
    orr     r0, r0, #ARM_CTRL_U                 ; allow unaligned accesses (codec optimization)
    mcr     p15, 0, r0, c1, c0, 0               ; update system control reg

    ;
    ; Configure ARM Peripheral Port Memory Remap Register (PPMRR)
    ;
    ldr     r0, =ARM_PPMRR_CONFIG               ; r0 = PPMRR configuration
    mcr     p15, 0, r0, c15, c2, 4              ; update PPMRR

    ; 
    ; Disable L2 cache
    ;
    ldr     r1, =CSP_BASE_REG_PA_L2CC
    ldr     r0, =0x0
    str     r0, [r1, #L2CC_CR_OFFSET]
    
    ;