intr.c

Freescale ARM11系列CPU MX31的WINCE 5.0下的BSP

//-----------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//-----------------------------------------------------------------------------
//
//  Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
//  THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
//  AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//-----------------------------------------------------------------------------
//
//  File:  intr.h
//
//  This file contains EVB board-specific interrupt code.
//
//-----------------------------------------------------------------------------
#include <cmnintrin.h>
#include "bsp.h"

extern UINT32 g_oalIrqTranslate[OAL_INTR_IRQ_MAXIMUM];
extern ULARGE_INTEGER g_oalIrqMask[OAL_INTR_IRQ_MAXIMUM];
extern g_oalGpioTranslate[DDK_GPIO_PORT3+1][GPIO_INTR_SOURCES_MAX];
extern g_oalGpioMask[DDK_GPIO_PORT3+1][OAL_INTR_IRQ_MAXIMUM];

extern PCSP_GPIO_REGS g_pGPIO1;
extern PCSP_PBC_REGS g_pPBC;

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrInit
//
BOOL BSPIntrInit()
{
    OALIntrStaticTranslate(SYSINTR_USBOTG, IRQ_USB_OTG);
    //OALMSG(1, (TEXT("KERNEL: Translate USB OTG =>irq(0x%x)->sysintr(0x%x)\r\n"), IRQ_USB_OTG, SYSINTR_USBOTG));

    // Add GPIO line interupt -> IRQ mapping.
    g_oalGpioTranslate[BSP_PBC_GPIO_PORT][BSP_PBC_GPIO_PIN] = BSP_PBC_IRQ;
    
    // Configure PBC interrupt line
    INSREG32(&g_pGPIO1->GDIR, GPIO_PIN_MASK(BSP_PBC_GPIO_PIN), 
        GPIO_PIN_VAL(GPIO_GDIR_INPUT, BSP_PBC_GPIO_PIN));

    INSREG32(&g_pGPIO1->ICR1, GPIO_ICR_MASK(BSP_PBC_GPIO_PIN), 
        GPIO_ICR_VAL(BSP_PBC_GPIO_LEVEL, BSP_PBC_GPIO_PIN));

    INSREG32(&g_pGPIO1->IMR, GPIO_PIN_MASK(BSP_PBC_GPIO_PIN), 
        GPIO_PIN_VAL(GPIO_IMR_UNMASKED, BSP_PBC_GPIO_PIN));

    return TRUE;
}

//------------------------------------------------------------------------------

BOOL BSPIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+BSPIntrRequestIrq(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n",
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    ));

    if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto cleanUp;

    switch (pDevLoc->IfcType)
    {
    case Internal:
        switch ((ULONG)pDevLoc->LogicalLoc)
        {
        case BSP_BASE_REG_PA_CS8900A_IOBASE:
            pIrqs[0] = BSP_CS8900_IRQ;
            *pCount = 1;
            rc = TRUE;
            break;
        }
        break;
    }

cleanUp:
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrRequestIrq(rc = %d)\r\n", rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrEnableIrq
//
//  This function is called from OALIntrEnableIrq to enable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrEnableIrq(UINT32 irq)
{
    UINT16 mask = 0;

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrEnableIrq(%d)\r\n", irq));

    // Create PBC interrupt mask based on IRQ
    switch(irq)
    {
    case BSP_CS8900_IRQ:
        mask = CSP_BITFMASK(PBC_INT_ENET);
        break;

    case BSP_USB_IRQ:
        mask = CSP_BITFMASK(PBC_INT_OTG_FS_OVR) | 
            CSP_BITFMASK(PBC_INT_FSH_OVR) | CSP_BITFMASK(PBC_INT_OTG_FS);
        break;
    }

    if (mask)
    {
        // Enable interrupts within PBC
        OUTREG16(&g_pPBC->INT_MASK_SET, mask);

        // Tell upper layers we dealt with BSP interrupt
        irq = OAL_INTR_IRQ_UNDEFINED;
    }
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrEnableIrq(irq = %d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDisableIrq
//
//  This function is called from OALIntrDisableIrq to disable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
    UINT16 mask = 0;
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));

    // Create PBC interrupt mask based on IRQ
    switch(irq)
    {
    case BSP_CS8900_IRQ:
        mask = CSP_BITFMASK(PBC_INT_ENET);
        break;

    case BSP_USB_IRQ:
        mask = CSP_BITFMASK(PBC_INT_OTG_FS_OVR) | 
            CSP_BITFMASK(PBC_INT_FSH_OVR) | CSP_BITFMASK(PBC_INT_OTG_FS);
        break;
    }

    if (mask)
    {
        // Disable interrupts within PBC
        OUTREG16(&g_pPBC->INT_MASK_CLEAR, mask);
        
        // Tell upper layers we dealt with BSP interrupt
        irq = OAL_INTR_IRQ_UNDEFINED;
    }

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDisableIrq(irq = %d\r\n", irq));
    return irq;
}


//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDoneIrq
//
//  This function is called from OALIntrDoneIrq to finish interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDoneIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDoneIrq(%d)\r\n", irq));
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDoneIrq(irq = %d)\r\n", irq));
    return BSPIntrEnableIrq(irq);
}


//------------------------------------------------------------------------------
//
//  Function:  BSPIntrActiveIrq
//
//  This function is called from interrupt handler to give BSP chance to
//  translate IRQ in case of secondary interrupt controller.
//
UINT32 BSPIntrActiveIrq(UINT32 irq)
{
    UINT32 line;
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrActiveIrq(%d)\r\n", irq));

    if (irq == BSP_PBC_IRQ)
    {
        irq = OAL_INTR_IRQ_UNDEFINED; 
                
        // Determine pending shared PBC interrupt source
        line = INREG16(&g_pPBC->INT_MASK_SET) & INREG16(&g_pPBC->INT_STATUS);

        line = _CountLeadingZeros(line);
            
        if (line < 32)
        {
            // If at least one GPIO interrupt line is asserted
            switch(31 - line)
            {
            case PBC_INT_ENET_LSH:
                irq = BSP_CS8900_IRQ;
                break;
                
            case PBC_INT_OTG_FS_OVR_LSH:
            case PBC_INT_FSH_OVR_LSH:
            case PBC_INT_OTG_FS_LSH:
                irq = BSP_USB_IRQ;
                break;

            }

            if (irq != OAL_INTR_IRQ_UNDEFINED) BSPIntrDisableIrq(irq);
        }

    }
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrActiveIrq(%d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------