📄 nandloader.s
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;
; Copyright (c) Microsoft Corporation. All rights reserved.
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; Copyright (C) 2003, MOTOROLA, INC. All Rights Reserved
; THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
; BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
; MOTOROLA, INC.
;
; Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
; THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
; AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
;
; File: EBOOT/NANDLOADER/nandloader.s
; Purpose: Implements the initial boot loader for NAND boot. It is
; automatically loader by NFC into a 2k RAM buffer upon startup.
; This copies the 256kB EBOOT into ram and jumps there.
;
; Notes: This bases on the assumption that block 0 is a good block.
;
; Author: Swee Yee Fonn
; Date: 03/23/2004
;
; Modifications:
; MM/DD/YYYY Initials Change description
;
AREA Init, CODE, READONLY, ALIGN=9 ; (ALIGN=9 needed for ALIGN 0x0200 below)
OPT 2 ; disable listing
INCLUDE registers.h
OPT 1 ; reenable listing
OPT 2 ; disable listing
INCLUDE nand.h
OPT 1 ; reenable listing
IRQDisable EQU 0x00000080
FIQDisable EQU 0x00000040
SVCMode EQU 0x00000013
; The following should not be changed unless memMap.h & config.bib &
; eboot.bib are changed!
; Flash/RAM/Vector Ram Physical base addresses
RamPABase EQU 0xA0000000 ; PA of RAM
VRamPABase EQU 0xFFFF4C00 ; PA of VRam
StackEndInVRamOffset EQU 0x0000B400 ; end of stack area offset
EbootInRamOffset EQU 0x00040000 ; start of EBOOT area
;
;------------------------------------------------------------------------------
; CODE AREA
;------------------------------------------------------------------------------
MAIN
EXPORT MAIN
;
; Exception vector table
;
b StartUp
ALIGN 0x20
;----------------------------------------------------------------------
; The table of exception handlers loaded by the exception vectors above.
StartUp_Addr DCD StartUp
LoopForever
b LoopForever
;----------------------------------------------------------------------
; The RESET entry point
StartUp
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;
; FUNCTION: StartUp
;
; DESCRIPTION: System bootstrap function
;
; PARAMETERS: None
;
; RETURNS: None
;
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Put the processor in supervisor mode
; Disable the interrupt request (IRQ) and fast interrupt request (FIQ)
; inputs
;--------------------------------------------------------------------------
mrs r0, cpsr ; r0 = CPSR
mov r0, #ARM_CPSR_MODE_SVC ; enter supervisor mode
orr r0, r0, #ARM_CPSR_IRQDISABLE ; disable normal IRQ
orr r0, r0, #ARM_CPSR_FIQDISABLE ; disable fast IRQ
msr cpsr_c, r0 ; update CPSR control bits
;--------------------------------------------------------------------------
; MS RECOMMENDATION:
; Disable memory management unit (MMU) and both the instruction and data
; caches
;--------------------------------------------------------------------------
mrc p15, 0, r0, c1, c0, 0 ; r0 = system control reg
bic r0, r0, #ARM_CTRL_ICACHE ; disable ICache
bic r0, r0, #ARM_CTRL_DCACHE ; disable DCache
bic r0, r0, #ARM_CTRL_MMU ; disable MMU
bic r0, r0, #ARM_CTRL_VECTORS ; set vector base to 0x00000000
mcr p15, 0, r0, c1, c0, 0 ; update system control reg
;
; Set up AIPI registers for module access.
; PSR[1:0]: 10 = 32bit, 01 = 16bit, 00 = 8bit.
; PAR: 1 = Supervisor access only, 0 = Access rights is up to peripheral.
; AAOR: 1 = Atomic access only, 0 = Accept non-atomic access.
;
; AIPI1 settings:
; PSR[0]: 0x20040304
; PSR[1]: 0xDFFBFCFB (16-bit: WDOG, KPP, OWIRE, I2C)
; PAR: 0x00000001
; AAOR: 0x00000001 (reset value)
;
ldr r1, =AIPI1_BASE
ldr r0, =0x20040304
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xDFFBFCFB
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_PAR_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_AAOR_OFFSET]
;
; AIPI2 settings:
; PSR[0]: 0x07FFC200
; PSR[1]: 0xFFFFFFFF
; PAR: 0xF8003D01
; AAOR: 0x00000001 (reset value)
;
ldr r1, =AIPI2_BASE
ldr r0, =0x07FFC200
str r0, [r1, #AIPI_PSR0_OFFSET]
ldr r0, =0xFFFFFFFF
str r0, [r1, #AIPI_PSR1_OFFSET]
ldr r0, =0xF8003D01
str r0, [r1, #AIPI_PAR_OFFSET]
ldr r0, =0x00000001
str r0, [r1, #AIPI_AAOR_OFFSET]
;
; Set up PLLCRC
;
ldr r0, =PLLCRC_BASE
ldr r1, =PLLCRC_PCDR_SETTING
str r1, [r0, #PLLCRC_PCDR0_OFFSET]
ldr r1, =PLLCRC_MPCTL0_SETTING
str r1, [r0, #PLLCRC_MPCTL0_OFFSET]
ldr r1, =PLLCRC_CSCR_SETTNG
str r1, [r0, #PLLCRC_CSCR_OFFSET]
; Wait for PLL lock
WaitForPLL
ldr r1, [r0, #PLLCRC_MPCTL1_OFFSET]
tst r1, #PLLCRC_MPCTL1_LF_SETTING
beq WaitForPLL
;
; Set up SYSCTRL for DDR
;
ldr r0, =SYSCTRL_BASE
ldr r1, =SYSCTRL_DSCR3_SETTING
str r1, [r0, #SYSCTRL_DSCR3_OFFSET]
ldr r1, =SYSCTRL_DSCR5_SETTING
str r1, [r0, #SYSCTRL_DSCR5_OFFSET]
ldr r1, =SYSCTRL_DSCR6_SETTING
str r1, [r0, #SYSCTRL_DSCR6_OFFSET]
ldr r1, =SYSCTRL_DSCR7_SETTING
str r1, [r0, #SYSCTRL_DSCR7_OFFSET]
ldr r1, =SYSCTRL_DSCR8_SETTING
str r1, [r0, #SYSCTRL_DSCR8_OFFSET]
;
; Set up ESDRAMC for DDR
;
ldr r1, =ESDRAMC_BASE
ldr r2, =RamPABase
; LPDDR delay line soft reset
ldr r0, =0x00000008
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Enable DDR operation
ldr r0, =0x00000004
str r0, [r1, #ESDRAMC_ESDMISC_OFFSET]
; Set DDR timing parameters
ldr r0, =0x00795429
str r0, [r1, #ESDRAMC_ESDCFG0_OFFSET]
; Set precharge command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Precharge command (1 << 28) = 0x10000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x92200000
ldr r0, =0x92200000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Access SDRAM with A10 high to precharge all banks
; Address used for mode, data ignored
ldr r0, =0x0
str r0, [r2, #0xF00]
; Set autorefresh command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Autorefresh command (2 << 28) = 0x20000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xA2200000
ldr r0, =0xA2200000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Use writes to refresh all banks of SDRAM
; Address used for mode, data ignored
ldr r0, =0x0
str r0, [r2]
str r0, [r2]
; Set load mode command
;
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Load mode command (3 << 28) = 0x30000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0xB2200000
ldr r0, =0xB2200000
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
; Use SDRAM write to load SDRAM mode register
; Address used for mode, data ignored
ldr r0, =0x0
strb r0, [r2, #0x33]
ldr r3, =(RamPABase + 0x01000000)
strb r0, [r3]
; Set normal mode command
;
; PRCT - 10 clocks to prechange (5 << 0) = 0x00000005
; BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080
; FP - No full page mode (0 << 8) = 0x00000000
; PWDT - Anytime no banks are active (1 << 10) = 0x00000400
; SREFR - 8 rows refreshed each clock (4 << 13) = 0x00008000
; DSIZ - 32-bit memory width (2 << 16) = 0x00020000
; COL - 10 column addresses (2 << 20) = 0x00200000
; ROW - 13 Row addresses (2 << 24) = 0x02000000
; SP - User mode access (0 << 27) = 0x00000000
; SMODE - Normal mode command (0 << 28) = 0x00000000
; SDE - Enable controller (1 << 31) = 0x80000000
; ------------
; 0x82228485
ldr r0, =0x82228485
str r0, [r1, #ESDRAMC_ESDCTL0_OFFSET]
;
; Set up stack in vector ram
;
ldr sp, =(VRamPABase + StackEndInVRamOffset - 4)
;
; Relocate to run in VRAM if need
;
IF RELOCATE_IPL_TO_VRAM
ldr r0, =VRamPABase
ldr r1, =NFC_BASE
mov r2, #(NFC_MAIN_RAM_BUF_SIZE / 16)
RelocateIPL
ldmia r1!, {r3-r6}
stmia r0!, {r3-r6}
subs r2, r2, #1
bne RelocateIPL
adr r0, RelocateIPLDone
ldr r1, =NFC_BASE
sub r0, r0, r1
ldr r1, =VRamPABase
add r0, r0, r1
mov pc, r0
RelocateIPLDone
ENDIF
; Load and boot SPL
b NandBoot
;******************************************************************************
;*
;* FUNCTION: NandBoot
;*
;* DESCRIPTION: Nand bootstrap function. Never returns.
;*
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