registers.h

Freescale ARM9系列CPU MX27的WINCE 5.0下的BSP

;
; Copyright (c) Microsoft Corporation.  All rights reserved.
;
; Use of this source code is subject to the terms of the Microsoft end-user
; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
; If you did not accept the terms of the EULA, you are not authorized to use
; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
; install media.
;
; Copyright (C) 2003, MOTOROLA, INC. All Rights Reserved
; THIS SOURCE CODE IS CONFIDENTIAL AND PROPRIETARY AND MAY NOT
; BE USED OR DISTRIBUTED WITHOUT THE WRITTEN PERMISSION OF
; MOTOROLA, INC.
;
; Copyright (C) 2004-2006, Freescale Semiconductor, Inc. All Rights Reserved.
; THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
; AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT

;
; File:     IPL/NANDLOADER/register.h
; Purpose:  Implements the required NAND access functions for copying EBOOT
;           into RAM.
;
; Notes:
;
; Author:   Swee Yee Fonn
; Date:     03/23/2004
;
; Modifications:
; MM/DD/YYYY        Initials    Change description
;

    IF :LNOT: :DEF: _EBOOT_NANDLOADER_REGISTERS_H
_NANDLOADER_REGISTERS_H     EQU     1


; Define to relocate IPL
    IF :LNOT: :DEF: RELOCATE_IPL_TO_VRAM
    GBLL        RELOCATE_IPL_TO_VRAM
RELOCATE_IPL_TO_VRAM    SETL    {TRUE}
    ENDIF

;-------------------------------------------------------------------------------
; ARM constants
;-------------------------------------------------------------------------------
ARM_CPSR_PRECISE            EQU     (1 << 8)
ARM_CPSR_IRQDISABLE         EQU     (1 << 7)
ARM_CPSR_FIQDISABLE         EQU     (1 << 6)
ARM_CPSR_MODE_SVC           EQU     0x13
ARM_CTRL_ICACHE             EQU     (1 << 12)
ARM_CTRL_DCACHE             EQU     (1 << 2)
ARM_CTRL_MMU                EQU     (1 << 0)
ARM_CTRL_VECTORS            EQU     (1 << 13)
ARM_CACR_FULL               EQU     0x3

;-------------------------------------------------------------------------------
; AIPI constants
;-------------------------------------------------------------------------------
AIPI1_BASE                  EQU     0x10000000
AIPI2_BASE                  EQU     0x10020000
AIPI_PSR0_OFFSET            EQU     0x0000
AIPI_PSR1_OFFSET            EQU     0x0004
AIPI_PAR_OFFSET             EQU     0x0008
AIPI_AAOR_OFFSET            EQU     0x000C

;-------------------------------------------------------------------------------
; PLLCRC constants
;-------------------------------------------------------------------------------
PLLCRC_BASE                 EQU     0x10027000
PLLCRC_CSCR_OFFSET          EQU     0x0000
PLLCRC_MPCTL0_OFFSET        EQU     0x0004
PLLCRC_MPCTL1_OFFSET        EQU     0x0008
PLLCRC_SPCTL0_OFFSET        EQU     0x000C
PLLCRC_SPCTL1_OFFSET        EQU     0x0010
PLLCRC_OSC26MCTL_OFFSET     EQU     0x0014
PLLCRC_PCDR0_OFFSET         EQU     0x0018
PLLCRC_PCDR1_OFFSET         EQU     0x001C
PLLCRC_PCCR0_OFFSET         EQU     0x0020
PLLCRC_PCCR1_OFFSET         EQU     0x0024

; Clock control register settings (FCLK/HCLK = 266MHz/133MHz)
PLLCRC_CSCR_SETTNG          EQU     0x33f40307
PLLCRC_MPCTL0_SETTING       EQU     0x04C22017
PLLCRC_MPCTL1_LF_SETTING    EQU     0x00008000

; Max divisor for all except NFC
PLLCRC_PCDR_SETTING         EQU     0xFFFF7FFF

;-------------------------------------------------------------------------------
; SYSCTRL constants
;-------------------------------------------------------------------------------
SYSCTRL_BASE                EQU     0x10027800
SYSCTRL_DSCR1_OFFSET        EQU     0x0020
SYSCTRL_DSCR2_OFFSET        EQU     0x0024
SYSCTRL_DSCR3_OFFSET        EQU     0x0028
SYSCTRL_DSCR4_OFFSET        EQU     0x002C
SYSCTRL_DSCR5_OFFSET        EQU     0x0030
SYSCTRL_DSCR6_OFFSET        EQU     0x0034
SYSCTRL_DSCR7_OFFSET        EQU     0x0038
SYSCTRL_DSCR8_OFFSET        EQU     0x003C
SYSCTRL_DSCR9_OFFSET        EQU     0x0040
SYSCTRL_DSCR10_OFFSET       EQU     0x0044
SYSCTRL_DSCR11_OFFSET       EQU     0x0048
SYSCTRL_DSCR12_OFFSET       EQU     0x004C
SYSCTRL_DSCR13_OFFSET       EQU     0x0050

; Driving strength setting for DDR
SYSCTRL_DSCR3_SETTING       EQU     0x55555555
SYSCTRL_DSCR5_SETTING       EQU     0x55555555
SYSCTRL_DSCR6_SETTING       EQU     0x55555555
SYSCTRL_DSCR7_SETTING       EQU     0x00005005
SYSCTRL_DSCR8_SETTING       EQU     0x15555555

;-------------------------------------------------------------------------------
; ESDRAMC constants
;-------------------------------------------------------------------------------
ESDRAMC_BASE                EQU     0xD8001000
ESDRAMC_ESDCTL0_OFFSET      EQU     0x0000
ESDRAMC_ESDCFG0_OFFSET      EQU     0x0004
ESDRAMC_ESDCTL1_OFFSET      EQU     0x0008
ESDRAMC_ESDCFG1_OFFSET      EQU     0x000C
ESDRAMC_ESDMISC_OFFSET      EQU     0x0010
    

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; NFC registers
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
NFC_BASE                        EQU     0xD8000000
NFC_MAIN_RAM_BUF1_OFFSET        EQU     (NFC_MAIN_BUF_SIZE)
NFC_MAIN_RAM_BUF2_OFFSET        EQU     (NFC_MAIN_RAM_BUF1_OFFSET + NFC_MAIN_BUF_SIZE)
NFC_MAIN_RAM_BUF3_OFFSET        EQU     (NFC_MAIN_RAM_BUF2_OFFSET + NFC_MAIN_BUF_SIZE)
NFC_SPARE_RAM_BUF0_OFFSET       EQU     (NFC_MAIN_RAM_BUF3_OFFSET + NFC_MAIN_BUF_SIZE)
NFC_SPARE_RAM_BUF1_OFFSET       EQU     (NFC_SPARE_RAM_BUF0_OFFSET + NFC_SPARE_BUF_SIZE)
NFC_SPARE_RAM_BUF2_OFFSET       EQU     (NFC_SPARE_RAM_BUF1_OFFSET + NFC_SPARE_BUF_SIZE)
NFC_SPARE_RAM_BUF3_OFFSET       EQU     (NFC_SPARE_RAM_BUF2_OFFSET + NFC_SPARE_BUF_SIZE)
NFC_MAIN_RAM_BUF_SIZE           EQU     (4 * NFC_MAIN_BUF_SIZE)

NFC_REGISTERS_OFFSET            EQU     0x00000E00
NFC_BUFSIZE_OFFSET              EQU     0x00
NFC_BLOCK_ADD_LOCK_OFFSET       EQU     0x02
NFC_RAM_BUFF_ADD_OFFSET         EQU     0x04
NFC_FLASH_ADD_OFFSET            EQU     0x06
NFC_FLASH_CMD_OFFSET            EQU     0x08
NFC_CONFIGURATION_OFFSET        EQU     0x0A
NFC_ECC_STATUS_RESULT_OFFSET    EQU     0x0C
NFC_ECC_STATUS_MAIN_OFFSET      EQU     0x0E
NFC_ECC_STATUS_SPARE_OFFSET     EQU     0x10
NFC_WRITE_PROT_OFFSET           EQU     0x12
NFC_UNLOCK_START_BLK_OFFSET     EQU     0x14
NFC_UNLOCK_END_BLK_OFFSET       EQU     0x16
NFC_WRITE_PROT_STAUS_OFFSET     EQU     0x18
NFC_CONFIG1_OFFSET              EQU     0x1A
NFC_CONFIG2_OFFSET              EQU     0x1C

; Register masks
; Configuration masks
NFC_BLS_UNLOCK                  EQU     0x0002

; ECC status register masks
NFC_ECC_ERM_NO_ERR              EQU     0x0000
NFC_ECC_ERM_1BIT_ERR            EQU     0x0001
NFC_ECC_ERM_UNRECV_ERR          EQU     0x0002
NFC_ECC_ERM_RESERVED            EQU     0x0003

; Config1 masks
NFC_CONFIG1_ECC_EN              EQU     0x0008
NFC_CONFIG1_SP_EN               EQU     0x0004

; Config2 masks
NFC_CONFIG2_INT                 EQU     0x8000
NFC_FDO_PAGE_READ               EQU     0x0008
NFC_FADD_ADDR_WRITE             EQU     0x0002
NFC_FCMD_CMD_WRITE              EQU     0x0001

; NFC buffer to use
NAND_BUFFER_IN_USE_ID           EQU     0x03
NFC_MAIN_BUFFER_IN_USE_ADDR     EQU     (NFC_BASE + NFC_MAIN_RAM_BUF3_OFFSET)
NFC_SPARE_BUFFER_IN_USE_ADDR    EQU     (NFC_BASE + NFC_SPARE_RAM_BUF3_OFFSET)

; NFC defines
NFC_MAIN_BUF_SIZE           EQU     512
NFC_SPARE_BUF_SIZE          EQU     16

    ENDIF

    END