📄 oal_startup.c
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{
GPIO_PORT port;
CSP_GPIO_REGS *pGPIO;
pGPIO = (CSP_GPIO_REGS *)CSP_BASE_REG_PA_GPIO;
// Software reset all ports.
for (port = GPIO_PORT_A; port < GPIO_PORT_MAX; port++)
OUTREG32(&pGPIO->PORT[port].SWR, GPIO_SWR_RESET);
#if 0
// Power on defaults
for (port = GPIO_PORT_A; port < GPIO_PORT_MAX; port++) {
switch (port) {
case GPIO_PORT_A:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFFFFFFFF);
break;
case GPIO_PORT_B:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFF3FFFF3);
break;
case GPIO_PORT_C:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFFFFFFFF);
break;
case GPIO_PORT_D:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFFFE0000);
break;
case GPIO_PORT_E:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFFFC0F27);
break;
case GPIO_PORT_F:
OUTREG32(&pGPIO->PORT[port].GIUS, 0xFF000000);
break;
}
OUTREG32(&pGPIO->PORT[port].DDIR, 0);
OUTREG32(&pGPIO->PORT[port].OCR1, 0);
OUTREG32(&pGPIO->PORT[port].OCR2, 0);
OUTREG32(&pGPIO->PORT[port].ICONFA1, 0xFFFFFFFF);
OUTREG32(&pGPIO->PORT[port].ICONFA2, 0xFFFFFFFF);
OUTREG32(&pGPIO->PORT[port].ICONFB1, 0xFFFFFFFF);
OUTREG32(&pGPIO->PORT[port].ICONFB2, 0xFFFFFFFF);
OUTREG32(&pGPIO->PORT[port].DR, 0);
OUTREG32(&pGPIO->PORT[port].ICR1, 0);
OUTREG32(&pGPIO->PORT[port].ICR2, 0);
OUTREG32(&pGPIO->PORT[port].IMR, 0);
OUTREG32(&pGPIO->PORT[port].GPR, 0);
OUTREG32(&pGPIO->PORT[port].PUEN, 0xFFFFFFFF);
}
#endif
// TODO: What pins need being enabled here??
// Enable default pins required by system.
// CLKO - PF15
OAL_IOMUX_PRI_PIN(pGPIO, GPIO_PORT_F, 15);
// RESET_OUT - PE17
OAL_IOMUX_PRI_PIN(pGPIO, GPIO_PORT_E, 17);
}
//------------------------------------------------------------------------------
//
// Function: OALInitWeim
//
// This function initializes Wireless External Interface Module (WEIM).
// Phyiscal address is used only.
//
// Parameters:
// None.
//
// Retruns:
// None.
//
//------------------------------------------------------------------------------
void OALInitWeim(void)
{
PCSP_WEIM_REGS pWeim = (PCSP_WEIM_REGS)CSP_BASE_REG_PA_WEIM;
//
// Synchronous read mode (HCLK = 133MHz; BCLK = 44.3MHz)
//
// Software reset command
*((REG16 *)CSP_BASE_MEM_PA_CS0) = 0x00F0;
// Write unlock cycles
*((REG16 *)CSP_BASE_MEM_PA_CS0 + 0x555) = 0x00AA;
*((REG16 *)CSP_BASE_MEM_PA_CS0 + 0x2AA) = 0x0055;
// Set configuration register
*((REG16 *)CSP_BASE_MEM_PA_CS0 + 0x555) = 0x00D0;
// *((REG16 *)CSP_BASE_MEM_PA_CS0 + 0xF00) = 0x56CA;
*((REG16 *)CSP_BASE_MEM_PA_CS0 + 0xF00) = 0x66CA; // 6th active clk
// Software reset command
*((REG16 *)CSP_BASE_MEM_PA_CS0) = 0x00F0;
//
// Configure CS0 for NOR Flash
//
// CS0 control (upper)
// EDC - 3 extra dead cycles (3 << 0) = 0x00000003
// WWS - 0 extra write wait states (0 << 4) = 0x00000000
// EW - Posedge DTACK (0 << 7) = 0x00000000
// WSC - 12 wait states (12 << 8) = 0x00000C00
// CNC - 3 CS negation cycles (3 << 14) = 0x0000C000
// DOL - 0 clock burst latency (0 << 16) = 0x00000000
// SYNC - Disable sync burst (0 << 20) = 0x00000000
// PME - Disable page mode (0 << 21) = 0x00000000
// PSZ - 4 word burst/page (0 << 22) = 0x00000000
// BCS - 1 BCLK delay (0 << 24) = 0x00000000
// BCD - /1 burst clock (0 << 28) = 0x00000000
// WP - No write protect (0 << 30) = 0x00000000
// SP - All user mode access (0 << 31) = 0x00000000
// ------------
// 0x0000CC03
// pWeim->CSCR0U = 0x0000CC03;
pWeim->CSCR0U = 0x23524E80;
// CS0 control (lower)
// CSEN - Enable chip select (1 << 0) = 0x00000001
// WRAP - No wrap (0 << 1) = 0x00000000
// CRE - CRE pin 0 (0 << 2) = 0x00000000
// PSR - PSRAM mode disabled (0 << 3) = 0x00000000
// CSN - 2 AHB clocks (2 << 4) = 0x00000000
// DSZ - 16-bit DATA[15:0] (5 << 8) = 0x00000500
// EBC - Only write asserts EB (1 << 11) = 0x00000800
// CSA - 2 half AHB clocks (0 << 12) = 0x00000000
// EBWN - 3 half AHB clocks (3 << 16) = 0x00030000
// EBWA - 3 half AHB clocks (3 << 20) = 0x00300000
// OEN - 2 half AHB clocks (0 << 24) = 0x00000000
// OEA - 10 half AHB clocks (10 << 28) = 0xA0000000
// ------------
// 0xA0330D01
// pWeim->CSCR0L = 0xA0330D01;
pWeim->CSCR0L = 0x10000D03;
// CS0 control (additional)
// FCE - Data capture by AHB clk (0 << 0) = 0x00000000
// CNC2 - No CNC increase (0 << 1) = 0x00000000
// AGE - Disable ack glue logic (0 << 2) = 0x00000000
// WWU - Forbit wrap on write (0 << 3) = 0x00000000
// DCT - 2 AHB clocks (0 << 4) = 0x00000000
// DWW - wait states same as read (0 << 6) = 0x00000000
// LBA - 0 half AHB clock (0 << 8) = 0x00000000
// LBN - 2 half AHB clocks (2 << 10) = 0x00000800
// LAH - 3 half AHB clocks (2 << 13) = 0x00000000
// MUM - Non-muxed mode (0 << 14) = 0x00000000
// RWN - 2 half AHB clocks (2 << 16) = 0x00020000
// RWA - 2 half AHB clocks (2 << 20) = 0x00200000
// EBRN - 0 half AHB clocks (0 << 24) = 0x00000000
// EBRA - 0 half AHB clocks (0 << 28) = 0x00000000
// ------------
// 0x00220800
// pWeim->CSCR0A = 0x00220800;
pWeim->CSCR0A = 0x00720900;
//
// Configure CS4 for CPLD
//
pWeim->CSCR4U = 0x0000DCF6;
pWeim->CSCR4L = 0x444A4541;
pWeim->CSCR4A = 0x44443302;
// TODO: Still under verifying
// Configure CS5 for PSRAM
//
// pWeim->CSCR5U = 0x0000DCF6;
// pWeim->CSCR5L = 0x444A4541;
// pWeim->CSCR5A = 0x44443302;
}
//------------------------------------------------------------------------------
//
// Function: OALInitEsdramc
//
// This function initializes Enhanced SDRAM Controller for DDR.
// Phyiscal address is used only.
//
// Parameters:
// None.
//
// Retruns:
// None.
//
//------------------------------------------------------------------------------
void OALInitEsdramc(void)
{
int i;
PCSP_ESDRAMC_REGS pEsdramc = (PCSP_ESDRAMC_REGS)CSP_BASE_REG_PA_ESDRAMC;
// LPDDR delay line soft reset
pEsdramc->ESDMISC = 0x00000008;
//Hold for more than 200ns
for(i = 0; i < 0x10000; i ++);
// Enable DDR operation
pEsdramc->ESDMISC = 0x00000004;
// Set ESDCFG0
pEsdramc->ESDCFG0 = 0x00795729;
// Set precharge command
//
// COL - 10 column addresses (2 << 20) = 0x00200000
// ROW - 13 Row addresses (2 << 24) = 0x02000000
// SP - User mode access (0 << 27) = 0x00000000
// SMODE - Precharge command (1 << 28) = 0x10000000
// SDE - Enable controller (1 << 31) = 0x80000000
// ------------
// 0x92200000
pEsdramc->ESDCTL0 = 0x92200000;
// Access SDRAM with A10 high to precharge all banks
// Address used for mode, data ignored
*((REG32 *)(CSP_BASE_MEM_PA_CSD0 + 0xF00)) = 0;
// Set autorefresh command
//
// COL - 10 column addresses (2 << 20) = 0x00200000
// ROW - 13 Row addresses (2 << 24) = 0x02000000
// SP - User mode access (0 << 27) = 0x00000000
// SMODE - Autorefresh command (2 << 28) = 0x20000000
// SDE - Enable controller (1 << 31) = 0x80000000
// ------------
// 0xA2200000
pEsdramc->ESDCTL0 = 0xA2200000;
// Use writes to refresh all banks of SDRAM
// Address used for mode, data ignored
*((REG32 *)CSP_BASE_MEM_PA_CSD0) = 0;
*((REG32 *)CSP_BASE_MEM_PA_CSD0) = 0;
// Set load mode command
//
// COL - 10 column addresses (2 << 20) = 0x00200000
// ROW - 13 Row addresses (2 << 24) = 0x02000000
// SP - User mode access (0 << 27) = 0x00000000
// SMODE - Load mode command (3 << 28) = 0x30000000
// SDE - Enable controller (1 << 31) = 0x80000000
// ------------
// 0xB2200000
pEsdramc->ESDCTL0 = 0xB2200000;
// Use SDRAM write to load SDRAM mode register
// Address used for mode, data ignored
*((REG8 *)(CSP_BASE_MEM_PA_CSD0 + 0x33)) = 0;
*((REG8 *)(CSP_BASE_MEM_PA_CSD0 + 0x01000000)) = 0;
// Set normal mode command
//
// PRCT - 10 clocks to prechange (5 << 0) = 0x00000005
// BL - Burst of 8 for SDR/DDR (1 << 7) = 0x00000080
// FP - No full page mode (0 << 8) = 0x00000000
// PWDT - Anytime no banks are active (1 << 10) = 0x00000400
// SREFR - 8 rows refreshed each clock (4 << 13) = 0x00008000
// DSIZ - 32-bit memory width (2 << 16) = 0x00020000
// COL - 10 column addresses (2 << 20) = 0x00200000
// ROW - 13 Row addresses (2 << 24) = 0x02000000
// SP - User mode access (0 << 27) = 0x00000000
// SMODE - Normal mode command (0 << 28) = 0x00000000
// SDE - Enable controller (1 << 31) = 0x80000000
// ------------
// 0x82228485
pEsdramc->ESDCTL0 = 0x82228485;
}
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