oal_startup.c

Freescale ARM9系列CPU MX27的WINCE 5.0下的BSP

//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006,2007 Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------
//
// File: startup.c
//
// MX27 ADS board initialization code.
//
//------------------------------------------------------------------------------
#include <bsp.h>

//------------------------------------------------------------------------------
// External Functions

//------------------------------------------------------------------------------
// External Variables

//------------------------------------------------------------------------------
// Defines

//------------------------------------------------------------------------------
// Types

//------------------------------------------------------------------------------
// Global Variables

//------------------------------------------------------------------------------
// Local Variables

//------------------------------------------------------------------------------
//
// Function: OALInitSysCtrl
//
// Function is called by StartUp to set up system control module. Physical 
// addresses are to be used here.
//
// Parameters:
//      None.
//
// Returns:
//      None.
//
//------------------------------------------------------------------------------
void OALInitSysCtrl(void)
{
    CSP_SYSCTRL_REGS *pSYSCTRL = (CSP_SYSCTRL_REGS *)CSP_BASE_REG_PA_SYSCTRL;

   	//
    // PCSR: Priority Control and Select Regisger
    //
    pSYSCTRL->PCSR= 0x00000003;

    //
    // FMCR: configure the following bits
    //  SYSCTRL_FMCR_SDCS1_SEL_USE_CS3
    //  SYSCTRL_FMCR_UART4_RTS_CTL_PB31_AOUT
    //  SYSCTRL_FMCR_UART4_RXD_CTL_PB29_AOUT
    // Other bits use reset value, but new bits in MX27 (PC_xxx) is TBD!!
    //
    pSYSCTRL->FMCR = 0xFCFFFFC9; 


    //
    // CLOCK_GATING_EN = 1
    // USB_Burst_Override = 1
    // PP_Burst_Override = 1
    // DMA_Burst_Override =1
    //
    pSYSCTRL->GPCR = 0x708;

    //
    // WBCR: use reset value 0
    // Well Bias is not applied for the time being.
    //
    // pSYSCTRL->WBCR = ;

    //
    // DSCR1 ~ DSCR13: Driving Strength
    // TODO: Currently only set for DDR
    //
    // pSYSCTRL->DSCR1     = ;
    // pSYSCTRL->DSCR2     = ;
    pSYSCTRL->DSCR3     = 0x55555555;
    // pSYSCTRL->DSCR4     = ;
    pSYSCTRL->DSCR5     = 0x55555555;
    pSYSCTRL->DSCR6     = 0x55555555;
    pSYSCTRL->DSCR7     = 0x00005005;
    pSYSCTRL->DSCR8     = 0x15555555;
    // pSYSCTRL->DSCR9     = ;
    // pSYSCTRL->DSCR10    = ;
    // pSYSCTRL->DSCR11    = ;
    // pSYSCTRL->DSCR12    = ;
    // pSYSCTRL->DSCR13    = ;

    //
    // PSCR: Pull Strength
    //
    // pSYSCTRL->PSCR = ;

    //
    // PCSR: use reset value
    // m0 | m1 = 0x00000003
    //
    // pSYSCTRL->PSCR = ;

    //
    // DPTC (Dynamic Process Temperature Compensate)
    // This power saving feature is not applied.
    // PMCR, DCVR0 ~ DCVR3 all use reset values.
    //
    // pSYSCTRL->PMCR = ;
    // pSYSCTRL->DCVR0 = ;
    // pSYSCTRL->DCVR1 = ;
    // pSYSCTRL->DCVR2 = ;
    // pSYSCTRL->DCVR3 = ;
}    

//------------------------------------------------------------------------------
//
// Function: OALInitPll
//
// Function is called by StartUp to set up the BSP board level clock 
// frequencies. Physical addresses are to be used here.
//
// Parameters:
//      None.
//
// Returns:
//      None.
//
//------------------------------------------------------------------------------
void OALInitPll(void)
{
    CSP_PLLCRC_REGS *pPLLCRC = (CSP_PLLCRC_REGS *)CSP_BASE_REG_PA_CRM;

    // CSCR
      
    pPLLCRC->CSCR = (\
        CSP_BITFVAL(PLLCRC_CSCR_MPEN, PLLCRC_CSCR_MPEN_ENABLE) |
        CSP_BITFVAL(PLLCRC_CSCR_SPEN, PLLCRC_CSCR_SPEN_ENABLE) |
#if (BSP_OSC_SEL == BSP_OSC_32K)
        CSP_BITFVAL(PLLCRC_CSCR_FPM_EN, PLLCRC_CSCR_FPM_EN_ENABLE) |
        CSP_BITFVAL(PLLCRC_CSCR_OSC26M_DIS, PLLCRC_CSCR_OSC26M_DIS_DISABLE) |
#elif (BSP_OSC_SEL == BSP_OSC_26M)
        CSP_BITFVAL(PLLCRC_CSCR_FPM_EN, PLLCRC_CSCR_FPM_EN_ENABLE) |
        CSP_BITFVAL(PLLCRC_CSCR_OSC26M_DIS, PLLCRC_CSCR_OSC26M_DIS_ENABLE) |
#endif
        CSP_BITFVAL(PLLCRC_CSCR_OSC26M_DIV1P5, PLLCRC_CSCR_OSC26M_DIV1P5_DIV1) |
        CSP_BITFVAL(PLLCRC_CSCR_IPDIV, PLLCRC_CSCR_IPDIV_DIV2) |
        CSP_BITFVAL(PLLCRC_CSCR_BCLKDIV, BSP_CSCR_BCLKDIV) |
        CSP_BITFVAL(PLLCRC_CSCR_PRESC, BSP_CSCR_PRESC) |
#if (BSP_OSC_SEL == BSP_OSC_32K)
        CSP_BITFVAL(PLLCRC_CSCR_MCU_SEL, PLLCRC_CSCR_MCU_SEL_SRC_FPM) |
        CSP_BITFVAL(PLLCRC_CSCR_SP_SEL, PLLCRC_CSCR_SP_SEL_SRC_FPM) |
#elif (BSP_OSC_SEL == BSP_OSC_26M)
        CSP_BITFVAL(PLLCRC_CSCR_MCU_SEL, PLLCRC_CSCR_MCU_SEL_SRC_OSC26) |
        CSP_BITFVAL(PLLCRC_CSCR_SP_SEL, PLLCRC_CSCR_SP_SEL_SRC_OSC26) |
#endif
        CSP_BITFVAL(PLLCRC_CSCR_MSHC_SEL, PLLCRC_CSCR_MSHC_SEL_SRC_SPLL) |
        CSP_BITFVAL(PLLCRC_CSCR_H264_SEL, PLLCRC_CSCR_H264_SEL_SRC_MPLL) |
        CSP_BITFVAL(PLLCRC_CSCR_SSI1_SEL, PLLCRC_CSCR_SSI1_SEL_SRC_SPLL) |
        CSP_BITFVAL(PLLCRC_CSCR_SSI2_SEL, PLLCRC_CSCR_SSI2_SEL_SRC_SPLL) |
        CSP_BITFVAL(PLLCRC_CSCR_SD_CNT, PLLCRC_CSCR_SD_CNT_AFT_4TH_EDG) |
        CSP_BITFVAL(PLLCRC_CSCR_USB_DIV, BSP_CSCR_USB_DIV)
    );


    // MPLL
    pPLLCRC->MPCTL0 = (\
        CSP_BITFVAL(PLLCRC_MPCTL0_CPLM, PLLCRC_MPCTL0_CPLM_MODE_FOL) |
        CSP_BITFVAL(PLLCRC_MPCTL0_PD, BSP_MPCTL0_PD) |
        CSP_BITFVAL(PLLCRC_MPCTL0_MFI, BSP_MPCTL0_MFI) |
        CSP_BITFVAL(PLLCRC_MPCTL0_MFN, BSP_MPCTL0_MFN) |
        CSP_BITFVAL(PLLCRC_MPCTL0_MFD, BSP_MPCTL0_MFD)
    );

    // SPLL
    pPLLCRC->SPCTL0 = (\
        CSP_BITFVAL(PLLCRC_SPCTL0_CPLM, PLLCRC_SPCTL0_CPLM_MODE_FOL) |
        CSP_BITFVAL(PLLCRC_SPCTL0_PD, BSP_SPCTL0_PD) |
        CSP_BITFVAL(PLLCRC_SPCTL0_MFI, BSP_SPCTL0_MFI) |
        CSP_BITFVAL(PLLCRC_SPCTL0_MFN, BSP_SPCTL0_MFN) |
        CSP_BITFVAL(PLLCRC_SPCTL0_MFD, BSP_SPCTL0_MFD)
    );

    // Restart MPLL & SPLL
    pPLLCRC->CSCR |= (\
        CSP_BITFMASK(PLLCRC_CSCR_SPLL_RESTART) |
        CSP_BITFMASK(PLLCRC_CSCR_MPLL_RESTART) |
#if (BSP_OSC_SEL == BSP_OSC_32K)
        CSP_BITFVAL(PLLCRC_CSCR_MCU_SEL, PLLCRC_CSCR_MCU_SEL_SRC_FPM) |
        CSP_BITFVAL(PLLCRC_CSCR_SP_SEL, PLLCRC_CSCR_SP_SEL_SRC_FPM) |
#elif (BSP_OSC_SEL == BSP_OSC_26M)
        CSP_BITFVAL(PLLCRC_CSCR_MCU_SEL, PLLCRC_CSCR_MCU_SEL_SRC_OSC26) |
        CSP_BITFVAL(PLLCRC_CSCR_SP_SEL, PLLCRC_CSCR_SP_SEL_SRC_OSC26) |
#endif 
        CSP_BITFVAL(PLLCRC_CSCR_MPEN, PLLCRC_CSCR_MPEN_ENABLE) |
        CSP_BITFVAL(PLLCRC_CSCR_SPEN, PLLCRC_CSCR_SPEN_ENABLE)        
    );
    while (\
        !EXTREG32BF(&pPLLCRC->MPCTL1, PLLCRC_MPCTL1_LF) |
        !EXTREG32BF(&pPLLCRC->SPCTL1, PLLCRC_MPCTL1_LF)
    );


    // PCDR0
    pPLLCRC->PCDR0 = (\
        CSP_BITFVAL(PLLCRC_PCDR0_MSHCDIV, BSP_PCDR0_MSHCDIV) |
        CSP_BITFVAL(PLLCRC_PCDR0_H264DIV, BSP_PCDR0_H264DIV) |
        CSP_BITFVAL(PLLCRC_PCDR0_NFCDIV, BSP_PCDR0_NFCDIV) |
        CSP_BITFVAL(PLLCRC_PCDR0_SSI2DIV, BSP_PCDR0_SSI2DIV) |
        CSP_BITFVAL(PLLCRC_PCDR0_SSI1DIV, BSP_PCDR0_SSI1DIV)
    );

    // PCDR1                            
    pPLLCRC->PCDR1 = (\
        CSP_BITFVAL(PLLCRC_PCDR1_PERDIV1, BSP_PCDR1_PERDIV1) |
        CSP_BITFVAL(PLLCRC_PCDR1_PERDIV2, BSP_PCDR1_PERDIV2) |
        CSP_BITFVAL(PLLCRC_PCDR1_PERDIV3, BSP_PCDR1_PERDIV3) |
        CSP_BITFVAL(PLLCRC_PCDR1_PERDIV4, BSP_PCDR1_PERDIV4)
    );

    // TODO: What clocks need being enabled here??
    // PCCR0: DMA, GPIO
    // PCCR1: HCLK_BROM, HCLK_DMA, HCLK_EMI, PERCLK1~4
    pPLLCRC->PCCR0 = (
        CSP_BITFMASK(PLLCRC_PCCR0_DMA_EN) |
        CSP_BITFMASK(PLLCRC_PCCR0_GPIO_EN) 
    );
    pPLLCRC->PCCR1 = (\
        CSP_BITFMASK(PLLCRC_PCCR1_HCLK_BROM) |
        CSP_BITFMASK(PLLCRC_PCCR1_HCLK_DMA) |
        CSP_BITFMASK(PLLCRC_PCCR1_HCLK_EMI) |
        CSP_BITFMASK(PLLCRC_PCCR1_PERCLK1_EN) |
        CSP_BITFMASK(PLLCRC_PCCR1_PERCLK2_EN) |
        CSP_BITFMASK(PLLCRC_PCCR1_PERCLK3_EN) |
        CSP_BITFMASK(PLLCRC_PCCR1_PERCLK4_EN)
    );
}

//------------------------------------------------------------------------------
//
// Function: OALInitGpio
//
// The function is called by OALStartUp to initialise the GPIO pins to a known
// state. Physical addresses are to be used here.
//
// Parameters:
//      None
//
// Returns:
//      None
//
//------------------------------------------------------------------------------
void OALInitGpio(void)