intr.c

Freescale ARM9系列CPU MX27的WINCE 5.0下的BSP

//-----------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//-----------------------------------------------------------------------------
//
// Copyright (C) 2004-2006,2007 Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//-----------------------------------------------------------------------------
//
//  File:  intr.h
//
//  This file contains MX27 ADS board-specific interrupt code.
//
//-----------------------------------------------------------------------------
#include <cmnintrin.h>
#include "bsp.h"


extern PCSP_GPIO_REGS g_pGPIO;
extern PCSP_PBC_REGS g_pPBC;
extern BOOL g_bBSPIrq;


#define CARD_DET_MASK  0x7000                  //MX27 ADS support SD slot 1&2, default setting slot 3 card insert status
#define CARD_INT_DET_BIT_MASK 0xd000   //
#define CARD_INT_REM_BIT_MASK 0x61      //

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrInit
//
BOOL BSPIntrInit()
{

    /* disable the interrupt and clear the status */
    OUTREG16(&g_pPBC->INT_MASK_CLEAR, 0xFFFF);
    OUTREG16(&g_pPBC->INT_STATUS, 0xFFFF);
    
	// Configure the Board specific IRQ line
    OAL_IOMUX_INTR_PIN(g_pGPIO, BSP_PBC_GPIO_PORT, BSP_PBC_GPIO_PIN,BSP_PBC_GPIO_LEVEL);
	
    OALIntrStaticTranslate(SYSINTR_USBOTG, IRQ_USBOTG);
  
    return TRUE;
}

//------------------------------------------------------------------------------

BOOL BSPIntrRequestIrqs(DEVICE_LOCATION *pDevLoc, UINT32 *pCount, UINT32 *pIrqs)
{
    BOOL rc = FALSE;

    OALMSG(OAL_INTR&&OAL_FUNC, (
        L"+BSPIntrRequestIrq(0x%08x->%d/%d/0x%08x/%d, 0x%08x, 0x%08x)\r\n",
        pDevLoc, pDevLoc->IfcType, pDevLoc->BusNumber, pDevLoc->LogicalLoc,
        pDevLoc->Pin, pCount, pIrqs
    ));

    if (pIrqs == NULL || pCount == NULL || *pCount < 1) goto cleanUp;

    switch (pDevLoc->IfcType)
    {
    case Internal:
        switch ((ULONG)pDevLoc->LogicalLoc)
        {
        case BSP_BASE_REG_PA_CS8900A_IOBASE:
            pIrqs[0] = BSP_CS8900_IRQ;
            *pCount = 1;
            rc = TRUE;
            break;
        }
        break;
    }

cleanUp:
    OALMSG(OAL_INTR&&OAL_FUNC, (L"-BSPIntrRequestIrq(rc = %d)\r\n", rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrEnableIrq
//
//  This function is called from OALIntrEnableIrq to enable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrEnableIrq(UINT32 irq)
{
    UINT16 mask = 0;

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrEnableIrq(%d)\r\n", irq));

    // Create PBC interrupt mask based on IRQ
    switch(irq)
    {
    case BSP_CS8900_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_ENET_INT);
        break;

    case BSP_USB_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_OTG_FS_OVR) | 
            CSP_BITFMASK(PBC_INT_MASK_FSH_OVR) | CSP_BITFMASK(PBC_INT_MASK_OTG_FS_INT);
        break;
		
    case BSP_FEC_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_FEC_INT);
        break;
        
    case BSP_LOW_BAT_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_LOW_BAT);
        break;
        
    case BSP_XUART_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_XUART_INT);
        break;
        
    case BSP_CCTL_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_CCTL1_2);
        break;
		
    case BSP_SDHC_MS_IRQ:
        irq = BSP_PBC_IRQ;
        break;

    default:
        break;

    }

    if (mask)
    {
        // Enable interrupts within PBC
        // Unmask the interrupt
        OUTREG16(&g_pPBC->INT_MASK_SET, mask);
        // Clear the interrupt status
        OUTREG16(&g_pPBC->INT_STATUS, mask);
        
        // Tell upper layers enable corresponding GPIO interrupt
        irq = BSP_PBC_IRQ;
    }
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrEnableIrq(irq = %d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDisableIrq
//
//  This function is called from OALIntrDisableIrq to disable interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDisableIrq(UINT32 irq)
{
    UINT16 mask = 0;
    
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDisableIrq(%d)\r\n", irq));

    // Create PBC interrupt mask based on IRQ
    switch(irq)
    {
    case BSP_CS8900_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_ENET_INT);
        break;

    case BSP_USB_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_OTG_FS_OVR) | 
            CSP_BITFMASK(PBC_INT_MASK_FSH_OVR) | CSP_BITFMASK(PBC_INT_MASK_OTG_FS_INT);
        break;
        
    case BSP_FEC_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_FEC_INT);
        break;
        
    case BSP_LOW_BAT_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_LOW_BAT);
        break;
        
    case BSP_XUART_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_XUART_INT);
        break;
        
    case BSP_CCTL_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_CCTL1_2);
        break;

    case BSP_SDHC_MS_IRQ:
        mask = CSP_BITFMASK(PBC_INT_MASK_SD1_R_EN) | CSP_BITFMASK(PBC_INT_MASK_SD2_R_EN) | CSP_BITFMASK(PBC_INT_MASK_SD3_R_EN) |
            CSP_BITFMASK(PBC_INT_MASK_MS_R_EN) | CSP_BITFMASK(PBC_INT_MASK_SD1_EN) | CSP_BITFMASK(PBC_INT_MASK_SD2_EN) | 
            CSP_BITFMASK(PBC_INT_MASK_SD3_EN) | CSP_BITFMASK(PBC_INT_MASK_MS_EN) ;
        break;  
        
    default:
        break;
    }

    if (mask)
    {
        // Disable interrupts within PBC
        OUTREG16(&g_pPBC->INT_MASK_CLEAR, mask);
		
        // Tell upper layers we dealt with BSP interrupt
        irq = OAL_INTR_IRQ_UNDEFINED;
    }

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDisableIrq(irq = %d\r\n", irq));
    return irq;
}


//------------------------------------------------------------------------------
//
//  Function:  BSPIntrDoneIrq
//
//  This function is called from OALIntrDoneIrq to finish interrupt on
//  secondary interrupt controller.
//
UINT32 BSPIntrDoneIrq(UINT32 irq)
{
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrDoneIrq(%d)\r\n", irq));
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrDoneIrq(irq = %d)\r\n", irq));
    return BSPIntrEnableIrq(irq);
}

//------------------------------------------------------------------------------
//
//  Function:  BSPIntrActiveIrq
//
//  This function is called from interrupt handler to give BSP chance to
//  translate IRQ in case of secondary interrupt controller.
//
UINT32 BSPIntrActiveIrq(UINT32 irq)
{
    UINT32 line;
	UINT32 intmastset;
    UINT16 carddetect;	
 	
    g_bBSPIrq = FALSE;

    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"+BSPIntrActiveIrq(%d)\r\n", irq));


    if (irq == BSP_PBC_IRQ)
    {   
        g_bBSPIrq = TRUE;
        irq = OAL_INTR_IRQ_UNDEFINED;

        // Determine pending shared PBC interrupt source
        intmastset = INREG16(&g_pPBC->INT_MASK_SET);
        line = intmastset & INREG16(&g_pPBC->INT_STATUS);
        line = _CountLeadingZeros(line);
        if (line < 32)
        {
            // If at least one GPIO interrupt line is asserted
            switch(31 - line)
            {
            case PBC_INT_ENET_INT_LSH:
                irq = BSP_CS8900_IRQ;
                break;
                
            case PBC_INT_OTG_FS_OVR_LSH:
            case PBC_INT_FSH_OVR_LSH:
            case PBC_INT_OTG_FS_INT_LSH:
                irq = BSP_USB_IRQ;
                break;
                
            case PBC_INT_FEC_INT_LSH:
                irq = BSP_FEC_IRQ;
                break;
                
            case PBC_INT_LOW_BAT_LSH:
                irq = BSP_LOW_BAT_IRQ;
                break;
                
            case PBC_INT_XUART_INT_LSH:
                irq = BSP_XUART_IRQ;
                break;


            case PBC_INT_CCTL1_2_LSH:
                irq = BSP_CCTL_IRQ;
                break;	 
				
            default:
                irq = OAL_INTR_IRQ_UNDEFINED;
                break;
            }
        } 
        else{
			// Support ONLY one card used at any time
            carddetect = INREG16(&g_pPBC->BSTAT1);
            carddetect &= CARD_DET_MASK;
			
            // Because of the CPLD interrupt design defect, the external 
            // Ethenet interrupt status can clear automatically before we
            // have chance to process if the CPU is very busy, in which 
            // case we can enter this location.
            // Since only one card is used, We can use the following simple logic to 
            // check if the interrupt is valid. 
            if(((carddetect == CARD_DET_MASK) && (intmastset & CARD_INT_REM_BIT_MASK))||
               ((carddetect != CARD_DET_MASK) && (intmastset & CARD_INT_DET_BIT_MASK)))
                irq = BSP_SDHC_MS_IRQ;
            else 
                irq = OAL_INTR_IRQ_UNDEFINED;
        }
		
        if (irq != OAL_INTR_IRQ_UNDEFINED) BSPIntrDisableIrq(irq);
    }
 
    OALMSG(OAL_INTR&&OAL_VERBOSE, (L"-BSPIntrActiveIrq(%d)\r\n", irq));
    return irq;
}

//------------------------------------------------------------------------------