nandfc.c

Freescale ARM9系列CPU MX27的WINCE 5.0下的BSP

//------------------------------------------------------------------------------
//
// Copyright (c) Microsoft Corporation.  All rights reserved.
//
//
// Use of this source code is subject to the terms of the Microsoft end-user
// license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
// If you did not accept the terms of the EULA, you are not authorized to use
// this source code. For a copy of the EULA, please see the LICENSE.RTF on your
// install media.
//
//------------------------------------------------------------------------------
//
// Copyright (C) 2004-2006,2007 Freescale Semiconductor, Inc. All Rights Reserved.
// THIS SOURCE CODE, AND ITS USE AND DISTRIBUTION, IS SUBJECT TO THE TERMS
// AND CONDITIONS OF THE APPLICABLE LICENSE AGREEMENT
//
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
//
//  Module: nandfc.c
//
//  NANDFC Driver services.
//
//------------------------------------------------------------------------------


//------------------------------------------------------------------------------
// INCLUDE FILES  
//------------------------------------------------------------------------------
#include "bsp.h"

//------------------------------------------------------------------------------
// GLOBAL DEFINITIONS  
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// GLOBAL OR STATIC VARIABLES  
//------------------------------------------------------------------------------
extern PBSP_ARGS g_pBSPARGS;        // From debug.c

//------------------------------------------------------------------------------
// STATIC FUNCTION PROTOTYPES  
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// EXPORTED FUNCTIONS
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
//
//  FUNCTION:       OALNandFCSetCfg
//
//  DESCRIPTION:    Configures the NANDFC to NAND flash interface as per 
//                  desired configuration.
//
//  PARAMETERS:     pInfo - contains flash info like access width,
//                          page size and max clock supported.
//
//  RETURNS:        BOOL for success/failure
//
//------------------------------------------------------------------------------
BOOL OALNandFCSetCfg(NANDFC_IOCTL_CFG *pCfg)
{
    CSP_PLLCRC_REGS *pPLLCRC;
    CSP_SYSCTRL_REGS *pSYSCTRL;
    BOOL rc = FALSE;
    UINT32 FclkFreq;
    UINT32 divisor;
    UINT32 clock;
    
    OALMSG(OAL_IOCTL&&OAL_FUNC, (TEXT("+OALNandFCSetCfg\r\n")));

    pPLLCRC = (CSP_PLLCRC_REGS *)OALPAtoUA(CSP_BASE_REG_PA_CRM);
    pSYSCTRL = (CSP_SYSCTRL_REGS *)OALPAtoUA(CSP_BASE_REG_PA_SYSCTRL);

    // Get the FCLK frequency from BSP_ARGS
    FclkFreq = g_pBSPARGS->clockFreq[DDK_CLOCK_SIGNAL_ARM];

    // Set required NFC clock divisor in PCDR
    clock = pCfg->clock;
    OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Desired clock(%d)\r\n"), clock));
    divisor = FclkFreq / clock;
    if( (FclkFreq % clock) > 0)
        divisor++;

    if(divisor > (CSP_BITFMASK(PLLCRC_PCDR0_NFCDIV) + 1))
        divisor = CSP_BITFMASK(PLLCRC_PCDR0_NFCDIV) + 1;

    OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: divisor(%d)\r\n"), divisor));
    OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Actual clock(%d)\r\n"), 
                                    (FclkFreq / (divisor+1)) ));
    INSREG32BF(&pPLLCRC->PCDR0, PLLCRC_PCDR0_NFCDIV, divisor-1);

    // Set page size if needed
    if(pCfg->page2048 == FALSE && 
        EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS) != SYSCTRL_FMCR_NF_FMS_512B_PAGE)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Set 512b page.\r\n")));
        INSREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS, SYSCTRL_FMCR_NF_FMS_512B_PAGE);
    }
    else if(pCfg->page2048 == TRUE && 
        EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS) != SYSCTRL_FMCR_NF_FMS_2KB_PAGE)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Set 2048b page.\r\n")));
        INSREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS, SYSCTRL_FMCR_NF_FMS_2KB_PAGE);
    }
    
    // Set flash access width if needed.
    if(pCfg->access16Bit == FALSE && 
        EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_16BIT_SEL) != SYSCTRL_FMCR_NF_16BIT_SEL_8BIT)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Set 8bit access.\r\n")));
        INSREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS, SYSCTRL_FMCR_NF_16BIT_SEL_8BIT);
    }
    else if(pCfg->access16Bit == TRUE && 
        EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_16BIT_SEL) != SYSCTRL_FMCR_NF_16BIT_SEL_16BIT)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCSetCfg: Set 16bit access.\r\n")));
        INSREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS, SYSCTRL_FMCR_NF_16BIT_SEL_16BIT);
    }
    rc = TRUE;
    
    OALMSG(OAL_IOCTL&&OAL_FUNC, (TEXT("-OALNandFCSetCfg: (rc = %d)\r\n"), rc));
    return rc;
}

//------------------------------------------------------------------------------
//
//  FUNCTION:       OALNandFCGetCfg
//
//  DESCRIPTION:    Returns the current NANDFC to NAND flash interface  
//                  configuration.
//
//  PARAMETERS:     pCfg - contains flash info like access width,
//                          page size and max clock supported.
//
//  RETURNS:        BOOL for success/failure
//
//------------------------------------------------------------------------------
BOOL OALNandFCGetCfg(NANDFC_IOCTL_CFG *pCfg)
{
    CSP_PLLCRC_REGS *pPLLCRC;
    CSP_SYSCTRL_REGS *pSYSCTRL;
    BOOL rc = FALSE;
    UINT32 FclkFreq;
    UINT32 divisor;
    
    OALMSG(OAL_IOCTL&&OAL_FUNC, (TEXT("+OALNandFCGetCfg\r\n")));

    pPLLCRC = (CSP_PLLCRC_REGS *)OALPAtoUA(CSP_BASE_REG_PA_CRM);
    pSYSCTRL = (CSP_SYSCTRL_REGS *)OALPAtoUA(CSP_BASE_REG_PA_SYSCTRL);

    // Get the FCLK frequency from BSP_ARGS
    FclkFreq = g_pBSPARGS->clockFreq[DDK_CLOCK_SIGNAL_ARM];

    // Get current NFC clock
    divisor = EXTREG32BF(&pPLLCRC->PCDR0, PLLCRC_PCDR0_NFCDIV) + 1;
    pCfg->clock = FclkFreq / divisor;

    OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: divisor(%d)\r\n"), divisor));
    OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: Actual clock(%d)\r\n"), 
                                    pCfg->clock ));
    INSREG32BF(&pPLLCRC->PCDR0, PLLCRC_PCDR0_NFCDIV, divisor);

    // Get page size configuration
    if(EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_FMS) == SYSCTRL_FMCR_NF_FMS_512B_PAGE)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: 512b page.\r\n")));
        pCfg->page2048 = FALSE;
    }
    else 
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: 2048b page.\r\n")));
        pCfg->page2048 = TRUE;
    }
    
    // Get flash access width configuration.
    if(EXTREG32BF(&pSYSCTRL->FMCR, SYSCTRL_FMCR_NF_16BIT_SEL) == SYSCTRL_FMCR_NF_16BIT_SEL_8BIT)
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: 8bit access.\r\n")));
        pCfg->access16Bit = FALSE;
    }
    else
    {
        OALMSG(OAL_IOCTL&&OAL_VERBOSE, (TEXT("OALNandFCGetCfg: 16bit access.\r\n")));
        pCfg->access16Bit = TRUE;
    }
    rc = TRUE;
    
    OALMSG(OAL_IOCTL&&OAL_FUNC, (TEXT("-OALNandFCGetCfg: (rc = %d)\r\n"), rc));
    return rc;
}

//------------------------------------------------------------------------------
// PRIVATE FUNCTIONS
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// END OF FILE
//------------------------------------------------------------------------------