bmd_64_tx_engine.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

          rmrd_count        <= 16'b0;

          serv_mwr          <= 1'b1;
          serv_mrd          <= 1'b1;

          bmd_64_tx_state   <= `BMD_64_TX_RST_STATE;

        end else begin


          if (init_rst_i ) begin

            trn_tsof_n        <= 1'b1;
            trn_teof_n        <= 1'b1;
            trn_tsrc_rdy_n    <= 1'b1;
            trn_tsrc_dsc_n    <= 1'b1;
            trn_td            <= 64'b0;
            trn_trem_n        <= 8'b0;

            cur_mwr_dw_count  <= 10'b0;

            compl_done_o      <= 1'b0;
            mwr_done_o        <= 1'b0;

            mrd_done          <= 1'b0;

            cur_wr_count      <= 16'b0;
            cur_wr_not1st     <= 1'b0;
            cur_rd_count      <= 16'b0;
            cur_rd_not1st     <= 1'b0;

            mwr_len_byte      <= 12'b0;
            mrd_len_byte      <= 12'b0;

            pmwr_addr         <= 32'b0;
            pmrd_addr         <= 32'b0;

            rmwr_count        <= 16'b0;
            rmrd_count        <= 16'b0;

            serv_mwr          <= 1'b1;
            serv_mrd          <= 1'b1;

            bmd_64_tx_state   <= `BMD_64_TX_RST_STATE;

          end

          mwr_len_byte        <= 4 * mwr_len_i[9:0];
          mrd_len_byte        <= 4 * mrd_len_i[9:0];
//          rmwr_count          <= mwr_count_i[15:0] ;
          rmwr_count          <= mwr_count_i[15:0] - 1'b1;
//          rmrd_count          <= mrd_count_i[15:0];
          rmrd_count          <= mrd_count_i[15:0] - 1'b1;

          case ( bmd_64_tx_state )

            `BMD_64_TX_RST_STATE : begin

              compl_done_o       <= 1'b0;

              // PIO read completions always get highest priority

              if (req_compl_q &&
                  !compl_done_o &&
                  trn_tdst_dsc_n) begin

                trn_tsof_n       <= 1'b0;
                trn_teof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b0;
                trn_td           <= { {1'b0},
                                      `BMD_64_CPLD_FMT_TYPE,
                                      {1'b0},
                                      req_tc_i,
                                      {4'b0},
                                      req_td_i,
                                      req_ep_i,
                                      req_attr_i,
                                      {2'b0},
                                      req_len_i,
                                      completer_id_i,
                                      {3'b0},
                                      {1'b0},
                                      byte_count };
                trn_trem_n        <= 8'b0;

                bmd_64_tx_state   <= `BMD_64_TX_CPLD_QW1;

              end else if (mwr_start_i &&
                           !mwr_done_o &&
                           serv_mwr &&
                           trn_tdst_dsc_n &&
                           cfg_bm_en) begin

                trn_tsof_n       <= 1'b0;
                trn_teof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b0;
                trn_td           <= { {1'b0},
                                      `BMD_64_MWR_FMT_TYPE,
                                      {1'b0},
                                      req_tc_i,
                                      {4'b0},
                                      1'b0,
                                      1'b0,
                                      2'b00,
                                      {2'b0},
                                      mwr_len_i[9:0],
                                      completer_id_i,
                                      cfg_ext_tag_en_i ? cur_wr_count[7:0]
                                                       : {3'b0, cur_wr_count[4:0]},
                                      (mwr_len_i[9:0] == 1'b1) ? 4'b0 : mwr_lbe_i,
                                      mwr_fbe_i};
                trn_trem_n        <= 8'b0;
                cur_mwr_dw_count  <= mwr_len_i[9:0];

                // Round robin
                if (mrd_start_i && !mrd_done) begin
                  serv_mwr        <= 1'b0;
                  serv_mrd        <= 1'b1;
                end else begin
                  serv_mwr        <= 1'b1;
                  serv_mrd        <= 1'b0;
                end
          if (cur_wr_not1st == 1'b0)                
                pmwr_addr <= mwr_addr;
        bmd_64_tx_state   <= `BMD_64_TX_MWR_QW1;

              end else if (mrd_start_i &&
                           !mrd_done &&
                           serv_mrd &&
                           trn_tdst_dsc_n &&
                           cfg_bm_en) begin

                trn_tsof_n       <= 1'b0;
                trn_teof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b0;
                trn_td           <= { {1'b0},
                                      `BMD_64_MRD_FMT_TYPE,
                                      {1'b0},
                                      req_tc_i,
                                      {4'b0},
                                      1'b0,
                                      1'b0,
                                      2'b00,
                                      {2'b0},
                                      mrd_len_i[9:0],
                                      completer_id_i,
                                      cfg_ext_tag_en_i ? cur_rd_count[7:0]
                                                       : {3'b0, cur_rd_count[4:0]},
                                      mrd_lbe_i,
                                      mrd_fbe_i};
                trn_trem_n        <= 8'b0;

                // Round robin
                if (mwr_start_i && !mwr_done_o) begin
                  serv_mwr        <= 1'b1;
                  serv_mrd        <= 1'b0;
                end else begin
                  serv_mwr        <= 1'b0;
                  serv_mrd        <= 1'b1;
                end
                if (cur_rd_not1st == 1'b0)
                  pmrd_addr        <= mrd_addr;
        bmd_64_tx_state   <= `BMD_64_TX_MRD_QW1;

              end else begin

                trn_tsof_n        <= 1'b1;
                trn_teof_n        <= 1'b1;
                trn_tsrc_rdy_n    <= 1'b1;
                trn_tsrc_dsc_n    <= 1'b1;
                trn_td            <= 64'b0;
                trn_trem_n        <= 8'b0;

                bmd_64_tx_state   <= `BMD_64_TX_RST_STATE;

              end

            end

            `BMD_64_TX_CPLD_QW1 : begin

              if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin

                trn_tsof_n       <= 1'b1;
                trn_teof_n       <= 1'b0;
                trn_tsrc_rdy_n   <= 1'b0;
                trn_td           <= { req_rid_i,
                                      req_tag_i,
                                      {1'b0},
                                      lower_addr,
                                      rd_data_i };
                trn_trem_n       <= 8'h00;
                compl_done_o     <= 1'b1;

                bmd_64_tx_state  <= `BMD_64_TX_CPLD_WIT;

              end else if (!trn_tdst_dsc_n) begin

                trn_tsrc_dsc_n   <= 1'b0;

                bmd_64_tx_state  <= `BMD_64_TX_CPLD_WIT;

              end else
                bmd_64_tx_state  <= `BMD_64_TX_CPLD_QW1;

            end

            `BMD_64_TX_CPLD_WIT : begin

              if ( (!trn_tdst_rdy_n) || (!trn_tdst_dsc_n) ) begin

                trn_tsof_n       <= 1'b1;
                trn_teof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b1;
                trn_tsrc_dsc_n   <= 1'b1;

                bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;

              end else
                bmd_64_tx_state  <= `BMD_64_TX_CPLD_WIT;

            end

            `BMD_64_TX_MWR_QW1 : begin

              if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin

                trn_tsof_n       <= 1'b1;
                trn_tsrc_rdy_n   <= 1'b0;
//                if (cur_wr_count == 0)
//                  tmwr_addr       = mwr_addr;
//                else
//                  tmwr_addr       = pmwr_addr + mwr_len_byte;
//                trn_td           <= {{tmwr_addr[31:2], 2'b00}, mwr_data_i};
//                pmwr_addr        <= tmwr_addr;

                trn_td           <= {{pmwr_addr[31:2], 2'b00}, mwr_data_i};
                pmwr_addr        <= pmwr_addr + mwr_len_byte;


//                if (cur_wr_count == (rmwr_count - 1'b1))  begin
                if (cur_wr_count == rmwr_count)  begin

                  cur_wr_count  <= 0;
                  mwr_done_o    <= 1'b1;
                  cur_wr_not1st <= 1'b0;
                end else begin
                  cur_wr_not1st <= 1'b1;
                  cur_wr_count  <= cur_wr_count + 1'b1;
                end
                if (cur_mwr_dw_count == 1'h1) begin

                  trn_teof_n       <= 1'b0;
                  cur_mwr_dw_count <= cur_mwr_dw_count - 1'h1;
                  trn_trem_n       <= 8'h00;
                  bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;

                end else begin

                  cur_mwr_dw_count <= cur_mwr_dw_count - 1'h1;
                  trn_trem_n       <= 8'hFF;
                  bmd_64_tx_state  <= `BMD_64_TX_MWR_QWN;

                end

              end else if (!trn_tdst_dsc_n) begin

                bmd_64_tx_state    <= `BMD_64_TX_RST_STATE;
                trn_tsrc_dsc_n     <= 1'b0;

              end else
                bmd_64_tx_state    <= `BMD_64_TX_MWR_QW1;

            end

            `BMD_64_TX_MWR_QWN : begin

              if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin

                trn_tsrc_rdy_n   <= 1'b0;

                if (cur_mwr_dw_count == 1'h1) begin

                  trn_td           <= {mwr_data_i, 32'hd0_da_d0_da};
                  trn_trem_n       <= 8'h0F;
                  trn_teof_n       <= 1'b0;
                  cur_mwr_dw_count <= cur_mwr_dw_count - 1'h1;
                  bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;

                end else if (cur_mwr_dw_count == 2'h2) begin

                  trn_td           <= {mwr_data_i, mwr_data_i};
                  trn_trem_n       <= 8'h00;
                  trn_teof_n       <= 1'b0;
                  cur_mwr_dw_count <= cur_mwr_dw_count - 2'h2;
                  bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;

                end else begin

                  trn_td           <= {mwr_data_i, mwr_data_i};
                  trn_trem_n       <= 8'hFF;
                  cur_mwr_dw_count <= cur_mwr_dw_count - 2'h2;
                  bmd_64_tx_state  <= `BMD_64_TX_MWR_QWN;

                end

              end else if (!trn_tdst_dsc_n) begin

                bmd_64_tx_state    <= `BMD_64_TX_RST_STATE;
                trn_tsrc_dsc_n     <= 1'b0;

              end else
                bmd_64_tx_state    <= `BMD_64_TX_MWR_QWN;

            end

            `BMD_64_TX_MRD_QW1 : begin

              if ((!trn_tdst_rdy_n) && (trn_tdst_dsc_n)) begin

                trn_tsof_n       <= 1'b1;
                trn_teof_n       <= 1'b0;
                trn_tsrc_rdy_n   <= 1'b0;
//                if (cur_rd_count == 0)
//                  tmrd_addr       = mrd_addr;
//                else
//                  tmrd_addr       = pmrd_addr + mrd_len_byte;

//                trn_td           <= {{tmrd_addr[31:2], 2'b00}, 32'hd0_da_d0_da};
//                pmrd_addr        <= tmrd_addr;
                trn_trem_n       <= 8'h0F;

                pmrd_addr        <= pmrd_addr + mrd_len_byte;
                trn_td           <= {{pmrd_addr[31:2], 2'b00}, 32'hd0_da_d0_da};


//                if (cur_rd_count == (rmrd_count - 1'b1)) begin
                if (cur_rd_count == rmrd_count) begin

                  cur_rd_count   <= 0;
                  mrd_done       <= 1'b1;
                  cur_rd_not1st  <= 1'b0;
                end else begin
                  cur_rd_not1st  <= 1'b1;
                  cur_rd_count <= cur_rd_count + 1'b1;
                end

                bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;

              end else if (!trn_tdst_dsc_n) begin

                bmd_64_tx_state  <= `BMD_64_TX_RST_STATE;
                trn_tsrc_dsc_n   <= 1'b0;

              end else
                bmd_64_tx_state  <= `BMD_64_TX_MRD_QW1;

            end

          endcase

        end

    end

endmodule // BMD_64_TX_ENGINE