bmd_64_tx_engine.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//--            **************************************
//--            ** Copyright (C) 2005, Xilinx, Inc. **
//--            ** All Rights Reserved.             **
//--            **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: BMD_64_TX_ENGINE.v
//--
//-- Description: 64 bit Local-Link Transmit Unit.
//--
//--------------------------------------------------------------------------------

`timescale 1ns/1ns

`define BMD_64_CPLD_FMT_TYPE 7'b10_01010
`define BMD_64_MWR_FMT_TYPE  7'b10_00000
`define BMD_64_MRD_FMT_TYPE  7'b00_00000

`define BMD_64_TX_RST_STATE  7'b0000001
`define BMD_64_TX_CPLD_QW1   7'b0000010
`define BMD_64_TX_CPLD_WIT   7'b0000100
`define BMD_64_TX_MWR_QW1    7'b0001000
`define BMD_64_TX_MWR_QWN    7'b0010000
`define BMD_64_TX_MRD_QW1    7'b0100000
`define BMD_64_TX_MRD_QWN    7'b1000000

`define BMD_64_TX_INTR_RST   3'b000
`define BMD_64_TX_INTR_WIT   3'b001
`define BMD_64_TX_INTR_ACT   3'b010
`define BMD_64_TX_INTR_DUN   3'b100

module BMD_64_TX_ENGINE (

                        clk,
                        rst_n,

                        trn_td,
                        trn_trem_n,
                        trn_tsof_n,
                        trn_teof_n,
                        trn_tsrc_rdy_n,
                        trn_tsrc_dsc_n,
                        trn_tdst_rdy_n,
                        trn_tdst_dsc_n,

                        req_compl_i,
                        compl_done_o,

                        req_tc_i,
                        req_td_i,
                        req_ep_i,
                        req_attr_i,
                        req_len_i,
                        req_rid_i,
                        req_tag_i,
                        req_be_i,
                        req_addr_i,

                        // BMD Read Access

                        rd_addr_o,
                        rd_be_o,
                        rd_data_i,


                        // Initiator Reset

                        init_rst_i,

                        // Write Initiator

                        mwr_start_i,
                        mwr_len_i,
                        mwr_tag_i,
                        mwr_lbe_i,
                        mwr_fbe_i,
                        mwr_addr_i,
                        mwr_data_i,
                        mwr_count_i,
                        mwr_done_o,

                        // Read Initiator

                        mrd_start_i,
                        mrd_len_i,
                        mrd_tag_i,
                        mrd_lbe_i,
                        mrd_fbe_i,
                        mrd_addr_i,
                        mrd_count_i,
                        mrd_done_i,

                        cfg_interrupt_n_o,
                        cfg_interrupt_rdy_n_i,

                        cfg_interrupt_assert_n_o,
                        cfg_interrupt_di_o,
                        cfg_interrupt_do_i,
                        cfg_interrupt_mmenable_i,
                        cfg_interrupt_msienable_i,

                        completer_id_i,
                        cfg_ext_tag_en_i,
                        cfg_bus_mstr_enable_i,

                        int_src_rd_o,
                        int_src_wr_o,
                        int_clear_i

                        );

    input               clk;
    input               rst_n;

    output [63:0]       trn_td;
    output [7:0]        trn_trem_n;
    output              trn_tsof_n;
    output              trn_teof_n;
    output              trn_tsrc_rdy_n;
    output              trn_tsrc_dsc_n;
    input               trn_tdst_rdy_n;
    input               trn_tdst_dsc_n;

    input               req_compl_i;
    output              compl_done_o;

    input [2:0]         req_tc_i;
    input               req_td_i;
    input               req_ep_i;
    input [1:0]         req_attr_i;
    input [9:0]         req_len_i;
    input [15:0]        req_rid_i;
    input [7:0]         req_tag_i;
    input [7:0]         req_be_i;
    input [10:0]        req_addr_i;

    output [6:0]        rd_addr_o;
    output [3:0]        rd_be_o;
    input  [31:0]       rd_data_i;

    input               init_rst_i;

    input               mwr_start_i;
    input  [31:0]       mwr_len_i;
    input  [7:0]        mwr_tag_i;
    input  [3:0]        mwr_lbe_i;
    input  [3:0]        mwr_fbe_i;
    input  [31:0]       mwr_addr_i;
    input  [31:0]       mwr_data_i;
    input  [31:0]       mwr_count_i;
    output              mwr_done_o;

    input               mrd_start_i;
    input  [31:0]       mrd_len_i;
    input  [7:0]        mrd_tag_i;
    input  [3:0]        mrd_lbe_i;
    input  [3:0]        mrd_fbe_i;
    input  [31:0]       mrd_addr_i;
    input  [31:0]       mrd_count_i;
    input               mrd_done_i;

    output              cfg_interrupt_n_o;
    input               cfg_interrupt_rdy_n_i;
    output              cfg_interrupt_assert_n_o;
    output [7:0]        cfg_interrupt_di_o;
    input  [7:0]        cfg_interrupt_do_i;
    input  [2:0]        cfg_interrupt_mmenable_i;
    input               cfg_interrupt_msienable_i;

    input [15:0]        completer_id_i;
    input               cfg_ext_tag_en_i;
    input               cfg_bus_mstr_enable_i;

    output             int_src_rd_o;
    output             int_src_wr_o;
    input              int_clear_i;

    // Local registers



    reg [63:0]          trn_td;
    reg [7:0]           trn_trem_n;
    reg                 trn_tsof_n;
    reg                 trn_teof_n;
    reg                 trn_tsrc_rdy_n;
    reg                 trn_tsrc_dsc_n;

    reg [11:0]          byte_count;
    reg [06:0]          lower_addr;

    reg                 req_compl_q;

    reg [6:0]           bmd_64_tx_state;

    reg                 compl_done_o;
    reg                 mwr_done_o;

    reg                 mrd_done;

    reg [15:0]          cur_wr_count;
    reg                 cur_wr_not1st;
    reg [15:0]          cur_rd_count;
    reg                 cur_rd_not1st;

    reg [9:0]           cur_mwr_dw_count;

    reg [11:0]          mwr_len_byte;
    reg [11:0]          mrd_len_byte;

    reg [31:0]          pmwr_addr;
    reg [31:0]          pmrd_addr;

    reg [31:0]          tmwr_addr;
    reg [31:0]          tmrd_addr;

    reg [15:0]          rmwr_count;
    reg [15:0]          rmrd_count;

    reg                 serv_mwr;
    reg                 serv_mrd;

    // Local wires

    wire                cfg_bm_en = cfg_bus_mstr_enable_i;
    wire [31:0]         mwr_addr  = mwr_addr_i;
    wire [31:0]         mrd_addr  = mrd_addr_i;

    wire                int_clear =int_clear_i;

    /*
     * Present address and byte enable to memory module
     */

    assign rd_addr_o = req_addr_i[10:2];
    assign rd_be_o =   req_be_i[3:0];

    /*
     * Calculate byte count based on byte enable
     */

    always @ (rd_be_o) begin

      casex (rd_be_o[3:0])

        4'b1xx1 : byte_count = 12'h004;
        4'b01x1 : byte_count = 12'h003;
        4'b1x10 : byte_count = 12'h003;
        4'b0011 : byte_count = 12'h002;
        4'b0110 : byte_count = 12'h002;
        4'b1100 : byte_count = 12'h002;
        4'b0001 : byte_count = 12'h001;
        4'b0010 : byte_count = 12'h001;
        4'b0100 : byte_count = 12'h001;
        4'b1000 : byte_count = 12'h001;
        4'b0000 : byte_count = 12'h001;

      endcase

    end

    /*
     * Calculate lower address based on  byte enable
     */

    always @ (rd_be_o or req_addr_i) begin

      casex (rd_be_o[3:0])

        4'b0000 : lower_addr = {req_addr_i[6:2], 2'b00};
        4'bxxx1 : lower_addr = {req_addr_i[6:2], 2'b00};
        4'bxx10 : lower_addr = {req_addr_i[6:2], 2'b01};
        4'bx100 : lower_addr = {req_addr_i[6:2], 2'b10};
        4'b1000 : lower_addr = {req_addr_i[6:2], 2'b11};

      endcase

    end

    always @ ( posedge clk or negedge rst_n ) begin

        if (!rst_n ) begin

          req_compl_q <= 1'b0;

        end else begin

          req_compl_q <= req_compl_i;

        end

    end

    /*
     *  Interrupt Controller
     */

    BMD_INTR_CTRL BMD_INTR_CTRL  (

                  .clk(clk),                   // I
                  .rst_n(rst_n),               // I

                  .init_rst_i(init_rst_i),     // I

                  .mrd_done_i(mrd_done_i),     // I
                  .mwr_done_i(mwr_done_o),     // I

                  .cfg_interrupt_rdy_n_i(cfg_interrupt_rdy_n_i), // I
                  .cfg_interrupt_n_o(cfg_interrupt_n_o),          //O

                  .cfg_interrupt_assert_n_o(cfg_interrupt_assert_n_o),  //O
                  .cfg_interrupt_di_o(cfg_interrupt_di_o), // O
                  .cfg_interrupt_do_i(cfg_interrupt_do_i),   //  I
                  .cfg_interrupt_mmenable_i(cfg_interrupt_mmenable_i), //  I
                  .cfg_interrupt_msienable_i(cfg_interrupt_msienable_i),  // I

                  .int_src_rd_o(int_src_rd_o),   // O
                  .int_src_wr_o(int_src_wr_o),   // O
                  .int_clear_i(int_clear)      // I

                  );


    /*
     *  Tx State Machine
     */

    always @ ( posedge clk or negedge rst_n ) begin

        if (!rst_n ) begin

          trn_tsof_n        <= 1'b1;
          trn_teof_n        <= 1'b1;
          trn_tsrc_rdy_n    <= 1'b1;
          trn_tsrc_dsc_n    <= 1'b1;
          trn_td            <= 64'b0;
          trn_trem_n        <= 8'b0;

          cur_mwr_dw_count  <= 10'b0;

          compl_done_o      <= 1'b0;
          mwr_done_o        <= 1'b0;

          mrd_done          <= 1'b0;

          cur_wr_count      <= 16'b0;
          cur_wr_not1st     <= 1'b0;
          cur_rd_count      <= 16'b0;
          cur_rd_not1st     <= 1'b0;

          mwr_len_byte      <= 12'b0;
          mrd_len_byte      <= 12'b0;

          pmwr_addr         <= 32'b0;
          pmrd_addr         <= 32'b0;

          rmwr_count        <= 16'b0;