xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx50t-ff1136-1.ucf

已经在xilinx的ML555开发板上实现的PCIEx4的设计

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#
# File:  xilinx_pci_exp_blk_plus_4_lane_ep_xc5vlx50t-ff1136-1.ucf
#
# Use this file only with the device listed below.  Any other
# combination is invalid.  Do not modify this file except in
# regions designated for "User" constraints.
#
# Copyright (c) 2006 Xilinx, Inc.  All rights reserved.
#
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# Define Device, Package And Speed Grade
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CONFIG PART = XC5VLX50T-FF1136-1 ;

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# User Time Names / User Time Groups / Time Specs
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# User Physical Constraints
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# Pinout and Related I/O Constraints
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#
# SYS reset (input) signal.  The sys_reset_n signal should be
# obtained from the PCI Express interface if possible.  For
# slot based form factors, a system reset signal is usually
# present on the connector.  For cable based form factors, a
# system reset signal may not be available.  In this case, the
# system reset signal must be generated locally by some form of
# supervisory circuit.  You may change the IOSTANDARD and LOC
# to suit your requirements and VCCO voltage banking rules.
#

NET "sys_reset_n"      LOC = "AE14"  | IOSTANDARD = LVCMOS25 | PULLUP | NODELAY ;

#
# SYS clock 100 MHz (input) signal. The sys_clk_p and sys_clk_n
# signals are the PCI Express reference clock. Virtex-5 GTP
# Transceiver architecture requires the use of a dedicated clock
# resources (FPGA input pins) associated with each GTP Transceiver Tile.
# To use these pins an IBUFDS primitive (refclk_ibuf) is
# instantiated in user's design.
# Please refer to the Virtex-5 GTP Transceiver User Guide
# (UG196) for guidelines regarding clock resource selection.
#

NET  "sys_clk_p"       LOC = "Y4"  ;
NET  "sys_clk_n"       LOC = "Y3"  ;
INST "refclk_ibuf"     DIFF_TERM = "TRUE" ;

#
# Transceiver instance placement.  This constraint selects the
# transceivers to be used, which also dictates the pinout for the
# transmit and receive differential pairs.  Please refer to the
# Virtex-5 GTP Transceiver User Guide (UG196) for more
# information.
#

# PCIe Lanes 0, 1
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i" LOC = GTP_DUAL_X0Y2;

# PCIe Lanes 2, 3
INST "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i" LOC = GTP_DUAL_X0Y1;


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# Physical Constraints
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#
# BlockRAM placement
#

INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y9 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst" LOC = RAMB36_X1Y8 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y7 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[0].ram_tdp2_inst" LOC = RAMB36_X1Y6 ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst"      LOC = RAMB36_X1Y5 ;

#
# Timing critical placements
#

INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/tx_bridge/tx_bridge/shift_pipe1" LOC = "SLICE_X59Y36" ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available" LOC = "SLICE_X58Y26" ;
INST "ep/BU2/U0/pcie_ep0/pcie_blk_if/cf_bridge/management_interface/mgmt_rdata_d1_3" LOC = "SLICE_X59Y25" ;

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# Timing Constraints
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#
# Ignore timing on asynchronous signals.
#

NET "sys_reset_n" TIG ;
NET "sys_clk_p"   TIG ;
NET "sys_clk_n"   TIG ;

#
# Timing requirements and related constraints.
#

NET "sys_clk_c"                                      PERIOD = 10ns;

NET "ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_refclk_out[0]" TNM_NET = "MGTCLK" ;


TIMESPEC "TS_MGTCLK"  = PERIOD "MGTCLK" 100.00 MHz HIGH 50 % ;

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# End
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