ep_mem.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

//--------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--
//--            **************************************
//--            ** Copyright (C) 2005, Xilinx, Inc. **
//--            ** All Rights Reserved.             **
//--            **************************************
//--
//--------------------------------------------------------------------------------
//-- Filename: EP_MEM.v
//--
//-- Description: Endpoint Memory: 8KB organized as 4 x (512 DW) BlockRAM banks. 
//--              Block RAM Port A: Read Port
//--              Block RAM Port B: Write Port
//--
//--------------------------------------------------------------------------------

`timescale 1ns/1ns

module EP_MEM (

                      clk_i,

                      a_rd_a_i_0,  // [8:0]
                      a_rd_d_o_0,  // [31:0]
                      a_rd_en_i_0,
    
                      b_wr_a_i_0,  // [8:0]
                      b_wr_d_i_0,  // [31:0]
                      b_wr_en_i_0,
                      b_rd_d_o_0,  // [31:0]
                      b_rd_en_i_0,
                  
                      a_rd_a_i_1,  // [8:0]
                      a_rd_d_o_1,  // [31:0]
                      a_rd_en_i_1,
    
                      b_wr_a_i_1,  // [8:0]
                      b_wr_d_i_1,  // [31:0]
                      b_wr_en_i_1,
                      b_rd_d_o_1,  // [31:0]
                      b_rd_en_i_1,

                      a_rd_a_i_2,  // [8:0]
                      a_rd_d_o_2,  // [31:0]
                      a_rd_en_i_2,
    
                      b_wr_a_i_2,  // [8:0]
                      b_wr_d_i_2,  // [31:0]
                      b_wr_en_i_2,
                      b_rd_d_o_2,  // [31:0]
                      b_rd_en_i_2,

                      a_rd_a_i_3,  // [8:0]
                      a_rd_d_o_3,  // [31:0]
                      a_rd_en_i_3,
    
                      b_wr_a_i_3,  // [8:0]
                      b_wr_d_i_3,  // [31:0]
                      b_wr_en_i_3,
                      b_rd_d_o_3,  // [31:0]
                      b_rd_en_i_3

                      );

    input             clk_i;
    
    input  [08:00]    a_rd_a_i_0;
    output [31:00]    a_rd_d_o_0;
    input             a_rd_en_i_0;
    
    input  [08:00]    b_wr_a_i_0;
    input  [31:00]    b_wr_d_i_0;
    input             b_wr_en_i_0;
    output [31:00]    b_rd_d_o_0;
    input             b_rd_en_i_0;

    input  [08:00]    a_rd_a_i_1;
    output [31:00]    a_rd_d_o_1;
    input             a_rd_en_i_1;
    
    input  [08:00]    b_wr_a_i_1;
    input  [31:00]    b_wr_d_i_1;
    input             b_wr_en_i_1;
    output [31:00]    b_rd_d_o_1;
    input             b_rd_en_i_1;

    input  [08:00]    a_rd_a_i_2;
    output [31:00]    a_rd_d_o_2;
    input             a_rd_en_i_2;
    
    input  [08:00]    b_wr_a_i_2;
    input  [31:00]    b_wr_d_i_2;
    input             b_wr_en_i_2;
    output [31:00]    b_rd_d_o_2;
    input             b_rd_en_i_2;

    input  [08:00]    a_rd_a_i_3;
    output [31:00]    a_rd_d_o_3;
    input             a_rd_en_i_3;
    
    input  [08:00]    b_wr_a_i_3;
    input  [31:00]    b_wr_d_i_3;
    input             b_wr_en_i_3;
    output [31:00]    b_rd_d_o_3;
    input             b_rd_en_i_3;

   RAMB36 #(
      .DOA_REG(1),  // Optional output registers on A port (0 or 1)
      .DOB_REG(1),  // Optional output registers on B port (0 or 1)
      .INIT_A(36'h000000000),  // Initial values on A output port
      .INIT_B(36'h000000000),  // Initial values on B output port
      .RAM_EXTENSION_A("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
      .RAM_EXTENSION_B("NONE"),  // "UPPER", "LOWER" or "NONE" when cascaded
      .READ_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
      .READ_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36
      .SIM_COLLISION_CHECK("ALL"),  // Collision check enable "ALL", "WARNING_ONLY",
                                    //   "GENERATE_X_ONLY" or "NONE
      .SRVAL_A(36'h000000000), // Set/Reset value for A port output
      .SRVAL_B(36'h000000000),  // Set/Reset value for B port output
      .WRITE_MODE_A("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
      .WRITE_MODE_B("WRITE_FIRST"),  // "WRITE_FIRST", "READ_FIRST", or "NO_CHANGE
      .WRITE_WIDTH_A(36),  // Valid values are 1, 2, 4, 9, 18, or 36
      .WRITE_WIDTH_B(36),  // Valid values are 1, 2, 4, 9, 18, or 36

      // The following INIT_xx declarations specify the initial contents of the RAM
      .INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
      .INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),