dsport_cfg.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

`endif // BOARDx08

  // Express User Ack Timeout override
  // -----------------------------------------------------------
  // Ack Timeout Override | cfg[447]   |       |              0 |
  // -----------------------------------------------------------
  // Ack Timout Value   | cfg[446:432] |       |           0204 |
  // -----------------------------------------------------------

  assign cfg[447] = 1'b0;
  assign cfg[446:432] = 15'h0204;

  // Express User Replay Timeout override
  // -----------------------------------------------------------
  // Replay Timeout Override | cfg[463] |       |             1 |
  // -----------------------------------------------------------
  // Replay Timout Value   | cfg[462:448] |       |        060d |
  // -----------------------------------------------------------

  assign cfg[463] = 1'b1;
  assign cfg[462:448] = 15'h060d;

  //***********************************************************//
  // Configuration bit setting information.                    // 
  //***********************************************************//
  //                                                           //
  // Reserved 			            cfg[501:464]               // 
  // PCI Config Space               cfg[502]                   // 
  // Extended Config Space          cfg[503]                   // 
  // Slot Clock Configure           cfg[504]                   // 
  // Two PLM Autoconfigure          cfg[506:505]               //
  // Fast train simulation          cfg[507]                   //
  // Trim TLP Digest ECRC           cfg[508]                   //
  // swap_ab_pairs                  cfg[509]                   //
  // Force Noscramble               cfg[510]                   //
  // calibration_block disable      cfg[511]                   //
  //***********************************************************//

  // Reserved
  assign cfg[501:464] = 36'b0;

  // PCI Configuration Space Access
  assign cfg[502] = 1'b0;

  // Extended Configuration Space Access
  assign cfg[503] = 1'b0;

  // Slot Clock Configure
  assign cfg[504] = 1'b1;

  // Two PLM Autoconfigure
  assign cfg[506:505]= 2'b00;

  // fast train simulation          
`ifdef SIMULATION
  assign cfg[507] = 1'b1;
`else
  `ifdef SIM_USERTB
    assign cfg[507] = 1'b1;
  `else
    assign cfg[507] = 1'b0;
  `endif
`endif

  // Trim TLP Digest ECRC.
  assign cfg[508] = 1'b0;

  // swap A-B pairs          
  assign cfg[509] = 1'b0;

  // Force No Scrambling.
  assign cfg[510] = 1'b0;

  // calibration block enable        
  assign cfg[511] = 1'b0;

  //***********************************************************//
  // Power Management Capabilities Register                    //
  // (byte offset 03-02H).                                     //
  // Section 3.2.3 PCI Bus PM Interface Specification v1.2     //
  // -----------------------------------------------------------
  // PME Support        | cfg[527:523] |       |         01111 | 
  //                    |              |                       |
  //                    |              |  D3cold = 1'b0        |
  //                    |              |  D3hot  = 1'b1        |
  //                    |              |  D2     = 1'b1        |
  //                    |              |  D1     = 1'b1        |
  //                    |              |  D0     = 1'b1        |
  // -----------------------------------------------------------
  // D2 Support         | cfg[522:522] |       |             1 |
  // -----------------------------------------------------------
  // D1 Support         | cfg[521:521] |       |             1 |
  // -----------------------------------------------------------
  // AUX Current        | cfg[520:518] |       |           000 |
  // -----------------------------------------------------------
  // DSI                | cfg[517:517] |       |             0 |
  // -----------------------------------------------------------
  // Reserved           | cfg[516:516] |       |             0 |
  // -----------------------------------------------------------
  // PME Clock          | cfg[515:515] |       |             0 |
  // -----------------------------------------------------------
  // Version            | cfg[514:512] |       |           010 |
  // -----------------------------------------------------------

  assign cfg[527:512] = 16'h7E03; 

  // -----------------------------------------------------------
  // Power consumed in D0 state.                              // 
  // -----------------------------------------------------------

  assign cfg[535:528] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power consumed in D0 state.             // 
  // Actual power consumed in D0 state :=                     //
  // Power consumed in D0 state * Scale Factor                // 
  // -----------------------------------------------------------

  assign cfg[543:536] = 8'h01; 

  // -----------------------------------------------------------
  // Power consumed in D1 state.                              // 
  // -----------------------------------------------------------

  assign cfg[551:544] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power consumed in D1 state.             //
  // Actual power consumed in D1 state :=                     //
  // Power consumed in D1 state * Scale Factor                //     
  // -----------------------------------------------------------

  assign cfg[559:552] = 8'h01; 

  // -----------------------------------------------------------
  // Power Consumed in D2 state.                              // 
  // -----------------------------------------------------------

  assign cfg[567:560] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power consumed in D2 state.             // 
  // Actual power consumed in D2 state :=                     // 
  // Power consumed in D2 state * Scale Factor                // 
  // -----------------------------------------------------------

  assign cfg[575:568] = 8'h01; 

  // -----------------------------------------------------------
  // Power Consumed in D3 state                               // 
  // -----------------------------------------------------------

  assign cfg[583:576] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power consumed in D3 state.             // 
  // Actual power consumed in D3 state :=                     // 
  // Power consumed in D2 state * Scale Factor                // 
  // -----------------------------------------------------------

  assign cfg[591:584] = 8'h01; 

  // -----------------------------------------------------------
  // Power Dissipated in D0 state.                            // 
  // -----------------------------------------------------------

  assign cfg[599:592] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power dissipated in D0 state.           //
  // Actual power dissipated in D0 state :=                   //
  // Power dissipated in D0 state * Scale Factor              //
  // -----------------------------------------------------------

   assign cfg[607:600] = 8'h01; 

  // -----------------------------------------------------------
  // Power Dissipated in D1 state.                            //
  // -----------------------------------------------------------

  assign cfg[615:608] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power dissipated in D1 state.           //
  // Actual power dissipated in D1 state :=                   //
  // Power dissipated in D1 state * Scale Factor              //   
  // -----------------------------------------------------------

  assign cfg[623:616] = 8'h01; 

  // -----------------------------------------------------------
  // Power Dissipated in D2 state.                            //
  // -----------------------------------------------------------

  assign cfg[631:624] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power dissipated in D2 state.           //
  // Actual power dissipated in D2 state :=                   //
  // Power dissipated in D2 state * Scale Factor              // 
  // -----------------------------------------------------------

  assign cfg[639:632] = 8'h01; 

  // -----------------------------------------------------------
  // Power Dissipated in D3 state.                            //
  // -----------------------------------------------------------

  assign cfg[647:640] = 8'h01; 

  // -----------------------------------------------------------
  // Scale Factor for power dissipated in D3 state.           //
  // Actual power dissipated in D3 state :=                   //
  // Power dissipated in D3 state * Scale Factor              // 
  // -----------------------------------------------------------

  assign cfg[655:648] = 8'h01; 

  //***********************************************************//
  // Device Serial Number Capabilities Serial Number Registers //
  // Section 7.12 PCI Express Base Specification v1.1          //
  //***********************************************************//
 
  // EUI-64 1st DW
  assign cfg[687:656] = 32'h0;

  // EUI-64 2nd DW
  assign cfg[719:688] = 32'h0;

  // RESERVED FOR FUTURE USE 
  assign cfg[1023:720] = 0;

endmodule