dsport_cfg.v

已经在xilinx的ML555开发板上实现的PCIEx4的设计

//------------------------------------------------------------------------------
//--
//-- This file is owned and controlled by Xilinx and must be used solely
//-- for design, simulation, implementation and creation of design files
//-- limited to Xilinx devices or technologies. Use with non-Xilinx
//-- devices or technologies is expressly prohibited and immediately
//-- terminates your license.
//--                    
//-- Xilinx products are not intended for use in life support
//-- appliances, devices, or systems. Use in such applications is
//-- expressly prohibited.
//--                    
//--            **************************************
//--            ** Copyright (C) 2005, Xilinx, Inc. **
//--            ** All Rights Reserved.             **
//--            **************************************
//--                    
//------------------------------------------------------------------------------
//-- Filename: dsport_cfg.v
//--                    
//-- Description:  PCI Express Endpoint Core Configuration File
//--                    
//--                    
//------------------------------------------------------------------------------

/**********************************************************************
  ** Note 1:
  Base Address Registers (BARs) settings contained in this file 
  are for demonstration purposes only. Users must review and change 
  these to suite their particular application.

  ** Note 2:
  Users may change setting values of the Read Only Capability
  registers to suite their application, but any change must comply
  with PCI Express Base Specification v1.1
 
  ** Note 3:
  Two PLM Autoconfigure setting (cfg[507:506]) must be set to 2'b00, 
  when interfacing the Endpoint Core with a PCIe compliant 
  Downstream Port. 

  ** Note 4:
  Values assigned to Reserved bits should not be changed.
***********************************************************************/

// Declare the module.

module dsport_cfg (cfg);


  // Declare the port directions.

  output [1023:0] cfg;


  //***********************************************************//
  // Configuration bit setting information.                    // 
  //***********************************************************//
  //                                                           //
  // vendor id                      cfg[ 15:  0]               // 
  // device id                      cfg[ 31: 16]               // 
  // revision id                    cfg[ 39: 32]               // 
  // class code                     cfg[ 63: 40]               // 
  // base address                   cfg[ 95: 64]               // 
  // base address                   cfg[127: 96]               // 
  // base address                   cfg[159:128]               // 
  // base address                   cfg[191:160]               // 
  // base address                   cfg[223:192]               // 
  // base address                   cfg[255:224]               // 
  // cardbus cis pointer            cfg[287:256]               // 
  // subsystem vendor id            cfg[303:288]               // 
  // subsystem id                   cfg[319:304]               // 
  // expansion rom bar              cfg[351:320]               // 
  //                                                           //
  //***********************************************************//


  // Vendor Identification.
  assign cfg[ 15:  0] = 16'h10ee;

  // Device Identification.
  assign cfg[ 31: 16] = 16'h0007;

  // Revision Identification.
  assign cfg[ 39: 32] = 8'h00;

  // Class Code.
  assign cfg[ 63: 40] = 24'h00_00_00;
 
  // BAR0. IO BAR 64KB aperture
  assign cfg[ 95: 64] = 32'hffff_0001;
 
  // BAR1. Mem 32 bit BAR 64KB aperture
  assign cfg[127: 96] = 32'hffff_0000;
 
  // BAR2. 
  assign cfg[159:128] = 32'hffff_0004;
 
  // BAR3. Mem 64 bit BAR 1MB BAR {BAR3,BAR2}
  assign cfg[191:160] = 32'hffff_ffff;
 
  // BAR4. 
  assign cfg[223:192] = 32'h0000_0000;
 
  // BAR5. 
  assign cfg[255:224] = 32'h0000_0000;
 
  // Cardbus CIS Pointer.
  assign cfg[287:256] = 32'h0000_0000;

  // Subvendor Identification.
  assign cfg[303:288] = 16'h10ee;

  // Subsystem Identification.
  assign cfg[319:304] = 16'h0007;

  // Expansion ROM BAR. Mem 32 bit BAR 4KB aperture
  assign cfg[351:320] = 32'hffff_f001;
 

  //***********************************************************//
  // Configuration bit setting information.                    // 
  //***********************************************************//
  //                                                           //
  // express capabilities           cfg[367:352]               // 
  // express device capabilities    cfg[399:368]               // 
  // express link capabilities      cfg[431:400]               // 
  // express ack timeout setting    cfg[447:432]               //
  // express replay timer setting   cfg[463:448]               //
  //                                                           //
  //***********************************************************//


  // Express Capabilities (byte offset 03H-02H).
  // -----------------------------------------------------------
  // RsvdP              | cfg[367:366] |       |            00 |
  // -----------------------------------------------------------
  // Interrupt Msg No.  | cfg[365:361] |       |         00000 |
  // -----------------------------------------------------------
  // Slot Implemented   | cfg[360:360] |       |             0 |
  // -----------------------------------------------------------
  // Dev/Port Type      | cfg[359:356] |       |          0000 |
  // -----------------------------------------------------------
  // Capability Version | cfg[355:352] |       |          0001 |
  // -----------------------------------------------------------

  assign cfg[367:352] = 16'h0001;

  // Express Device Capabilities (byte offset 07H-04H).
  // -----------------------------------------------------------
  // RsvdP              | cfg[399:396] |       |          0000 |
  // -----------------------------------------------------------
  // Capt Slt Pwr Lim Sc| cfg[395:394] |       |            00 |
  // -----------------------------------------------------------
  // Capt Slt Pwr Lim Va| cfg[393:386] |       |      00000000 |
  // -----------------------------------------------------------
  // RsvdP              | cfg[385:384] |       |            00 |
  // -----------------------------------------------------------
  // Role based error   | cfg[383]             |             1 |
  // -----------------------------------------------------------
  // Power Indi Prsnt   | cfg[382:382] |       |             0 |
  // -----------------------------------------------------------
  // Attn Indi Prsnt    | cfg[381:381] |       |             0 |
  // -----------------------------------------------------------
  // Attn Butn Prsnt    | cfg[380:380] |       |             0 |
  // -----------------------------------------------------------
  // EP L1 Accpt Lat    | cfg[379:377] |       |           111 |
  // -----------------------------------------------------------
  // EP L0s Accpt Lat   | cfg[376:374] |       |           111 |
  // -----------------------------------------------------------
  // Ext Tag Fld Sup    | cfg[373:373] |       |             0 |
  // -----------------------------------------------------------
  // Phantm Func Sup    | cfg[372:371] |       |            00 |
  // -----------------------------------------------------------
  // Max Payload Size   | cfg[370:368] | (x1)  |           010 |
  // Max Payload Size   | cfg[370:368] | (x4)  |           010 |
  // Max Payload Size   | cfg[370:368] | (x8)  |           001 |
  // -----------------------------------------------------------

`ifdef  BOARDx08

  assign cfg[399:368] = 32'h00008FC1;

`else // BOARDx04 or BOARDx01

`ifdef BOARDx04

  assign cfg[399:368] = 32'h00008FC2;

`else  // must be BOARDx01 

  assign cfg[399:368] = 32'h00008FC2;

`endif // BOARDx04

`endif // BOARDx08

  // Express Link Capabilities (byte offset 00H && 0CH-0FH).
  // -----------------------------------------------------------
  // PCI Express Cap ID | cfg[431:424] |       |      00010000 |
  // -----------------------------------------------------------
  // -----------------------------------------------------------
  // RsvdP              | cfg[423:418] |       |        000000 |
  // -----------------------------------------------------------
  // L1 Exit Lat        | cfg[417:415] |       |           111 |
  // -----------------------------------------------------------
  // L0s Exit Lat       | cfg[414:412] |       |           111 |
  // -----------------------------------------------------------
  // ASPM Supported     | cfg[411:410] |       |            01 |
  // -----------------------------------------------------------
  // Max Link Width     | cfg[409:404] | (x1)  |        000001 |
  // Max Link Width     | cfg[409:404] | (x4)  |        000100 |
  // Max Link Width     | cfg[409:404] | (x8)  |        001000 |
  // -----------------------------------------------------------
  // Max Link Speed     | cfg[403:400] |       |          0001 |
  // -----------------------------------------------------------

`ifdef  BOARDx08

  assign cfg[431:400] = 32'h1003F481;

`else // BOARDx04 or BOARDx01

`ifdef BOARDx04

  assign cfg[431:400] = 32'h1003F441;

`else  // must be BOARDx01 

  assign cfg[431:400] = 32'h1003F411;

`endif // BOARDx04