📄 pci_exp_usrapp_tx.v
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/************************************************************ Task : TSK_TX_MEMORY_WRITE_32 Inputs : Tag, Length, Address, Last Byte En, First Byte En Outputs : Transaction Tx Interface Signaling Description : Generates a Memory Write 32 TLP *************************************************************/ task TSK_TX_MEMORY_WRITE_32; input [7:0] tag_; input [2:0] tc_; input [9:0] len_; input [31:0] addr_; input [3:0] last_dw_be_; input [3:0] first_dw_be_; input ep_; reg [10:0] _len; integer _j; begin if (len_ == 0) _len = 1024; else _len = len_; if (trn_lnk_up_n) begin $display("[%t] : Trn interface is MIA", $realtime); $finish(1); end TSK_TX_SYNCHRONIZE(0, 0); trn_td <= #(Tcq) { 1'b0, 2'b10, 5'b00000, 1'b0, tc_, 4'b0000, 1'b0, 1'b0, 2'b00, 2'b00, len_, // 32 COMPLETER_ID_CFG, tag_, last_dw_be_, first_dw_be_ // 64 }; trn_tsof_n <= #(Tcq) 0; trn_teof_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 0 ; TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { addr_[31:2], 2'b00, DATA_STORE[0], DATA_STORE[1], DATA_STORE[2], DATA_STORE[3] }; trn_tsof_n <= #(Tcq) 1; if (_len != 1) begin for (_j = 4; _j < (_len * 4); _j = _j + 8) begin TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { DATA_STORE[_j + 0], DATA_STORE[_j + 1], DATA_STORE[_j + 2], DATA_STORE[_j + 3], DATA_STORE[_j + 4], DATA_STORE[_j + 5], DATA_STORE[_j + 6], DATA_STORE[_j + 7] }; if ((_j + 7) >= ((_len * 4) - 1)) begin trn_teof_n <= #(Tcq) 0; if (ep_) trn_terrfwd_n <= #(Tcq) 0; if (((_len - 1) % 2) == 0) trn_trem_n <= #(Tcq) 8'h00; else trn_trem_n <= #(Tcq) 8'h0f; end end end else begin trn_teof_n <= #(Tcq) 0; if (ep_) trn_terrfwd_n <= #(Tcq) 0; trn_trem_n <= #(Tcq) 8'h00; end TSK_TX_SYNCHRONIZE(1, 1); trn_teof_n <= #(Tcq) 1; trn_terrfwd_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 1; end endtask // TSK_TX_MEMORY_WRITE_32 /************************************************************ Task : TSK_TX_MEMORY_WRITE_64 Inputs : Tag, Length, Address, Last Byte En, First Byte En Outputs : Transaction Tx Interface Signaling Description : Generates a Memory Write 64 TLP *************************************************************/ task TSK_TX_MEMORY_WRITE_64; input [7:0] tag_; input [2:0] tc_; input [9:0] len_; input [63:0] addr_; input [3:0] last_dw_be_; input [3:0] first_dw_be_; input ep_; reg [10:0] _len; integer _j; begin if (len_ == 0) _len = 1024; else _len = len_; if (trn_lnk_up_n) begin $display("[%t] : Trn interface is MIA", $realtime); $finish(1); end TSK_TX_SYNCHRONIZE(0, 0); trn_td <= #(Tcq) { 1'b0, 2'b11, 5'b00000, 1'b0, tc_, 4'b0000, 1'b0, 1'b0, 2'b00, 2'b00, len_, // 32 COMPLETER_ID_CFG, tag_, last_dw_be_, first_dw_be_ // 64 }; trn_tsof_n <= #(Tcq) 0; trn_teof_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 0 ; TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { addr_[63:2], 2'b00 }; trn_tsof_n <= #(Tcq) 1; for (_j = 0; _j < (_len * 4); _j = _j + 8) begin TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { DATA_STORE[_j + 0], DATA_STORE[_j + 1], DATA_STORE[_j + 2], DATA_STORE[_j + 3], DATA_STORE[_j + 4], DATA_STORE[_j + 5], DATA_STORE[_j + 6], DATA_STORE[_j + 7] }; if ((_j + 7) >= ((_len * 4) - 1)) begin trn_teof_n <= #(Tcq) 0; if (ep_) trn_terrfwd_n <= #(Tcq) 0; if ((_len % 2) == 0) trn_trem_n <= #(Tcq) 8'h00; else trn_trem_n <= #(Tcq) 8'h0f; end end TSK_TX_SYNCHRONIZE(1, 1); trn_teof_n <= #(Tcq) 1; trn_terrfwd_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 1; end endtask // TSK_TX_MEMORY_WRITE_64 /************************************************************ Task : TSK_TX_COMPLETION Inputs : Tag, TC, Length, Completion ID Outputs : Transaction Tx Interface Signaling Description : Generates a Completion TLP *************************************************************/ task TSK_TX_COMPLETION; input [7:0] tag_; input [2:0] tc_; input [9:0] len_; input [2:0] comp_status_; begin if (trn_lnk_up_n) begin $display("[%t] : Trn interface is MIA", $realtime); $finish(1); end TSK_TX_SYNCHRONIZE(0, 0); trn_td <= #(Tcq) { 1'b0, 2'b00, 5'b01010, 1'b0, tc_, 4'b0000, 1'b0, 1'b0, 2'b00, 2'b00, len_, // 32 COMPLETER_ID_CFG, comp_status_, 1'b0, 12'b0 }; trn_tsof_n <= #(Tcq) 0; trn_teof_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 0 ; TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { COMPLETER_ID_CFG, tag_, 8'b00, 32'b0 }; trn_tsof_n <= #(Tcq) 1; trn_teof_n <= #(Tcq) 0; trn_trem_n <= #(Tcq) 8'h0F; TSK_TX_SYNCHRONIZE(1, 1); trn_teof_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 1; end endtask // TSK_TX_COMPLETION /************************************************************ Task : TSK_TX_COMPLETION_DATA Inputs : Tag, TC, Length, Completion ID Outputs : Transaction Tx Interface Signaling Description : Generates a Completion TLP *************************************************************/ task TSK_TX_COMPLETION_DATA; input [7:0] tag_; input [2:0] tc_; input [9:0] len_; input [11:0] byte_count_; input [6:0] lower_addr_; input [2:0] comp_status_; input ep_; reg [10:0] _len; integer _j; begin if (len_ == 0) _len = 1024; else _len = len_; if (trn_lnk_up_n) begin $display("[%t] : Trn interface is MIA", $realtime); $finish(1); end TSK_TX_SYNCHRONIZE(0, 0); trn_td <= #(Tcq) { 1'b0, 2'b10, 5'b01010, 1'b0, tc_, 4'b0000, 1'b0, 1'b0, 2'b00, 2'b00, len_, // 32 COMPLETER_ID_CFG, comp_status_, 1'b0, byte_count_ // 64 }; trn_tsof_n <= #(Tcq) 0; trn_teof_n <= #(Tcq) 1; trn_trem_n <= #(Tcq) 0; trn_tsrc_rdy_n <= #(Tcq) 0 ; TSK_TX_SYNCHRONIZE(1, 0); trn_td <= #(Tcq) { COMPLETER_ID_CFG, tag_, 1'b0,
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