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# Loading work.sys_clk_gen_ds(fast__1)# Loading work.sys_clk_gen(fast__1)# Loading work.glbl(fast)# ** Warning: (vsim-PLI-3003) ../board.v(123): [TOFD] - System task or function '$fsdbDumpfile' is not defined.# Region: /boardx04# ** Warning: (vsim-PLI-3003) ../board.v(124): [TOFD] - System task or function '$fsdbDumpvars' is not defined.# Region: /boardx04# ** Warning: (vsim-3015) /program/ise92/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i\/gtp_dual_swift_1# ** Warning: (vsim-3015) /program/ise92/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i\/gtp_dual_swift_1# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport# Runtime, SwiftPLI v1.13# Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED# Platform Type: linux (32-bit).# You can use the Browser tool to configure the SmartModel# Library and access information about SmartModels:# $LMC_HOME/bin/sl_browser# # SmartModel product documentation is available here:# $LMC_HOME/doc/smartmodel/manuals/intro.pdf# http://www.synopsys.com/products/lm/doc/smartmodel.html# # # Note: Model pcie_internal_1_1_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/pcie_ep .pcie_internal_1_1_swift_1.I1(PCIE_INTERNAL_1_1_SWIFT:pcie_internal_1_1_swift), at time 0.0 ns# # Note: Model gtp_dual_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i .gtp_dual_swift_1.I1(GTP_DUAL_SWIFT:gtp_dual_swift), at time 0.0 ns# # Note: Model gt11_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_downstream_port.xilinx_pci_exp_4_lane_dsport.pci_exp_4_lane_64b_dsport.plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.gt11_swift_1.I1(GT11_SWIFT:gt11_swift), at time 0.0 ns# Running test {sample_smoke_test0}......# [ 0] : System Reset Asserted...# [ 4995000] : System Reset De-asserted...# [ 8522100] : Transaction Reset Is De-asserted...# [ 80250100] : Transaction Link Is Up...# [ 80250100] : Expected Device/Vendor ID = 100010ee# [ 80250100] : Reading from PCI/PCI-Express Configuration Register 0x00# [ 80274000] : TSK_PARSE_FRAME on Transmit# [ 81874000] : TSK_PARSE_FRAME on Receive# [ 82674000] : TEST FAILED --- Data Error Mismatch, Write Data 100010ee != Read Data 425010ee# ** Note: $finish : ../tests/sample_tests1.v(30)# Time: 82674 ns Iteration: 11 Instance: /boardx04/xilinx_pci_exp_4_lane_downstream_port/tx_usrapp# 1# Break in Module pci_exp_usrapp_tx at ../tests/sample_tests1.v line 30do simulate_mti.do# ** Warning: (vlib-34) Library already exists at "work".# Reading modelsim.ini# "work" maps to directory work. (Default mapping)# Model Technology ModelSim SE vlog 6.2e Compiler 2006.11 Nov 16 2006# -- Compiling module novas_vlog# # Top level modules:# novas_vlog# Model Technology ModelSim SE vlog 6.2e Compiler 2006.11 Nov 16 2006# -- Compiling module BMD# -- Compiling module BMD_64_RX_ENGINE# -- Compiling module BMD_64_TX_ENGINE# -- Compiling module BMD_EP_MEM_ACCESS# -- Compiling module BMD_EP_MEM# -- Compiling module BMD_EP# -- Compiling module BMD_INTR_CTRL# -- Compiling module BMD_TO_CTRL# -- Compiling module xilinx_pci_exp_4_lane_ep# -- Compiling module pci_exp_64b_app# -- Compiling module endpoint_blk_plus_v1_5# -- Compiling module glbl# -- Compiling module boardx04# -- Compiling module xilinx_pci_exp_4_lane_downstream_port# -- Compiling module xilinx_pci_exp_4_lane_dsport# -- Compiling module dsport_cfg# -- Compiling module pci_exp_usrapp_rx# -- Compiling module pci_exp_usrapp_tx# -- Compiling module pci_exp_usrapp_com# -- Compiling module pci_exp_usrapp_cfg# -- Compiling module pci_exp_4_lane_64b_dsport# -- Compiling module sys_clk_gen# -- Compiling module sys_clk_gen_ds# -- Scanning library directory '/program/ise92/verilog/src/simprims'# -- Scanning library directory '/program/ise92/verilog/src/unisims'# -- Compiling module IBUFDS# -- Compiling module IBUF# -- Compiling module VCC# -- Compiling module GND# -- Compiling module INV# -- Compiling module LUT5# -- Compiling module LUT3# -- Compiling module LUT4# -- Compiling module FDR# -- Compiling module LUT2# -- Compiling module LUT6# -- Compiling module FDC# -- Compiling module FDCE# -- Compiling module FDP# -- Compiling module BUFG# -- Compiling module PLL_ADV# -- Compiling module PCIE_INTERNAL_1_1# -- Compiling module RAMB36_EXP# -- Compiling module RAMB36SDP_EXP# -- Compiling module FDRE# -- Compiling module GTP_DUAL# -- Compiling module LDP_1# -- Compiling module FD# -- Compiling module FDE# -- Compiling module SRLC16E# -- Compiling module MUXF7# -- Compiling module FDRS# -- Compiling module LUT1# -- Compiling module FDRSE# -- Compiling module FDS# -- Compiling module FDSE# -- Compiling module MUXCY# -- Compiling module XORCY# -- Compiling module RAM32X1D# -- Compiling module GT11CLK_MGT# -- Compiling module OBUF# -- Compiling module LUT4_L# -- Compiling module LUT1_L# -- Compiling module LUT2_L# -- Compiling module LUT3_L# -- Compiling module MUXF5# -- Compiling module FDPE# -- Compiling module BUF# -- Compiling module DCM_ADV# -- Compiling module dcm_adv_clock_divide_by_2# -- Compiling module dcm_adv_maximum_period_check# -- Compiling module dcm_adv_clock_lost# -- Compiling module BUFGMUX_VIRTEX4# -- Compiling module MUXCY_L# -- Compiling module SRLC16# -- Compiling module SRL16# -- Compiling module GT11# -- Compiling module RAM16X1D# -- Compiling module SRL16E# -- Compiling module RAMB16_S18_S18# -- Compiling module MULT_AND# -- Compiling module MUXF6# -- Compiling module ARAMB36_INTERNAL# -- Compiling module BUFGCTRL# -- Scanning library directory '/program/ise92/smartmodel/lin/wrappers/mtiverilog'# -- Compiling module PCIE_INTERNAL_1_1_SWIFT# -- Compiling module GTP_DUAL_SWIFT# -- Compiling module GT11_SWIFT# -- Compiling module PCIE_INTERNAL_1_1_SWIFT_BIT# -- Compiling module GTP_DUAL_SWIFT_BIT# -- Compiling module GT11_SWIFT_BIT# # Top level modules:# glbl# boardx04# vsim +notimingchecks +TESTNAME=sample_smoke_test0 -L work work.boardx04 glbl # ** Note: (vsim-3813) Design is being optimized due to module recompilation...# ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.# Loading /program/modeltech/linux/libswiftpli.sl# Loading work.glbl(fast)# Loading work.boardx04(fast)# Loading work.xilinx_pci_exp_4_lane_ep(fast)# Loading work.IBUFDS(fast)# Loading work.IBUF(fast)# Loading work.pci_exp_64b_app(fast)# Loading work.BMD(fast)# Loading work.BMD_EP(fast)# Loading work.BMD_EP_MEM_ACCESS(fast)# Loading work.BMD_EP_MEM(fast)# Loading work.BMD_64_RX_ENGINE(fast)# Loading work.BMD_64_TX_ENGINE(fast)# Loading work.BMD_INTR_CTRL(fast)# Loading work.BMD_TO_CTRL(fast)# Loading work.endpoint_blk_plus_v1_5(fast)# Loading work.VCC(fast)# Loading work.GND(fast)# Loading work.INV(fast)# Loading work.LUT5(fast)# Loading work.LUT3(fast)# Loading work.LUT4(fast)# Loading work.FDR(fast)# Loading work.LUT2(fast)# Loading work.LUT6(fast)# Loading work.LUT2(fast__1)# Loading work.LUT2(fast__2)# Loading work.LUT2(fast__3)# Loading work.LUT2(fast__4)# Loading work.FDC(fast)# Loading work.FDCE(fast)# Loading work.FDP(fast)# Loading work.BUFG(fast)# Loading work.PLL_ADV(fast)# Loading work.PCIE_INTERNAL_1_1(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT(fast)# Loading work.PCIE_INTERNAL_1_1_SWIFT_BIT(fast)# Loading work.RAMB36_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast)# Loading work.RAMB36SDP_EXP(fast)# Loading work.ARAMB36_INTERNAL(fast__1)# Loading work.FDRE(fast)# Loading work.GTP_DUAL(fast)# Loading work.GTP_DUAL_SWIFT(fast)# Loading work.GTP_DUAL_SWIFT_BIT(fast)# Loading work.GTP_DUAL(fast__1)# Loading work.LDP_1(fast)# Loading work.FD(fast)# Loading work.FD(fast__1)# Loading work.FDE(fast)# Loading work.SRLC16E(fast)# Loading work.MUXF7(fast)# Loading work.RAMB36SDP_EXP(fast__1)# Loading work.ARAMB36_INTERNAL(fast__2)# Loading work.LUT2(fast__5)# Loading work.LUT2(fast__6)# Loading work.FDRS(fast)# Loading work.LUT1(fast)# Loading work.FDRSE(fast)# Loading work.FDS(fast)# Loading work.LUT2(fast__7)# Loading work.FDSE(fast)# Loading work.FDRSE(fast__1)# Loading work.FDE(fast__1)# Loading work.MUXCY(fast)# Loading work.XORCY(fast)# Loading work.FDSE(fast__1)# Loading work.RAM32X1D(fast)# Loading work.xilinx_pci_exp_4_lane_downstream_port(fast)# Loading work.xilinx_pci_exp_4_lane_dsport(fast)# Loading work.GT11CLK_MGT(fast)# Loading work.OBUF(fast)# Loading work.pci_exp_4_lane_64b_dsport(fast)# Loading work.LUT1(fast__1)# Loading work.LUT2(fast__8)# Loading work.LUT4_L(fast)# Loading work.LUT1_L(fast)# Loading work.LUT2_L(fast)# Loading work.LUT2_L(fast__1)# Loading work.LUT2_L(fast__2)# Loading work.LUT3_L(fast)# Loading work.LUT2(fast__9)# Loading work.MUXF5(fast)# Loading work.LUT2_L(fast__3)# Loading work.LUT2_L(fast__4)# Loading work.LUT2_L(fast__5)# Loading work.FDPE(fast)# Loading work.BUF(fast)# Loading work.DCM_ADV(fast)# Loading work.dcm_adv_clock_divide_by_2(fast)# Loading work.dcm_adv_maximum_period_check(fast)# Loading work.dcm_adv_maximum_period_check(fast__1)# Loading work.dcm_adv_clock_lost(fast)# Loading work.BUFGMUX_VIRTEX4(fast)# Loading work.BUFGCTRL(fast)# Loading work.MUXCY_L(fast)# Loading work.LUT2_L(fast__6)# Loading work.SRLC16(fast)# Loading work.SRL16(fast)# Loading work.LUT1_L(fast__1)# Loading work.GT11(fast)# Loading work.GT11_SWIFT(fast)# Loading work.GT11_SWIFT_BIT(fast)# Loading work.GT11(fast__1)# Loading work.GT11(fast__2)# Loading work.LUT2_L(fast__7)# Loading work.RAM16X1D(fast)# Loading work.LUT2_L(fast__8)# Loading work.LUT2_L(fast__9)# Loading work.SRL16E(fast)# Loading work.RAMB16_S18_S18(fast)# Loading work.MULT_AND(fast)# Loading work.MUXF6(fast)# Loading work.dsport_cfg(fast)# Loading work.pci_exp_usrapp_rx(fast)# Loading work.pci_exp_usrapp_tx(fast)# Loading work.pci_exp_usrapp_cfg(fast)# Loading work.pci_exp_usrapp_com(fast)# Loading work.sys_clk_gen_ds(fast)# Loading work.sys_clk_gen(fast)# Loading work.sys_clk_gen_ds(fast__1)# Loading work.sys_clk_gen(fast__1)# ** Warning: (vsim-PLI-3003) ../board.v(123): [TOFD] - System task or function '$fsdbDumpfile' is not defined.# Region: /boardx04# ** Warning: (vsim-PLI-3003) ../board.v(124): [TOFD] - System task or function '$fsdbDumpvars' is not defined.# Region: /boardx04# ** Warning: (vsim-3015) /program/ise92/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i\/gtp_dual_swift_1# ** Warning: (vsim-3015) /program/ise92/verilog/src/unisims/GTP_DUAL.v(3471): [PCDPC] - Port size (9 or 9) does not match connection size (12) for port 'SIM_PLL_PERDIV2'.# Region: /boardx04/xilinx_pci_exp_4_lane_ep/ep/\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[0].GT_i\/gtp_dual_swift_1# ** Warning: (vsim-3015) ../dsport/xilinx_pci_exp_dsport.v(551): [PCDPC] - Port size (5 or 5) does not match connection size (3) for port 'trn_tbuf_av'.# Region: /boardx04/xilinx_pci_exp_4_lane_downstream_port/xilinx_pci_exp_4_lane_dsport/pci_exp_4_lane_64b_dsport# Runtime, SwiftPLI v1.13# Copyright (c) 1984-2007 Synopsys Inc. ALL RIGHTS RESERVED# Platform Type: linux (32-bit).# You can use the Browser tool to configure the SmartModel# Library and access information about SmartModels:# $LMC_HOME/bin/sl_browser# # SmartModel product documentation is available here:# $LMC_HOME/doc/smartmodel/manuals/intro.pdf# http://www.synopsys.com/products/lm/doc/smartmodel.html# # # Note: Model pcie_internal_1_1_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/pcie_ep .pcie_internal_1_1_swift_1.I1(PCIE_INTERNAL_1_1_SWIFT:pcie_internal_1_1_swift), at time 0.0 ns# # Note: Model gtp_dual_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_ep.ep.\BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/GTD[2].GT_i .gtp_dual_swift_1.I1(GTP_DUAL_SWIFT:gtp_dual_swift), at time 0.0 ns# # Note: Model gt11_swift: Model Vendor: `Xilinx'.# SmartModel Instance boardx04.xilinx_pci_exp_4_lane_downstream_port.xilinx_pci_exp_4_lane_dsport.pci_exp_4_lane_64b_dsport.plm_v4f_mgt_gt11_by4_GT11_PCIEXP_4_INST.gt11_swift_1.I1(GT11_SWIFT:gt11_swift), at time 0.0 ns# Running test {sample_smoke_test0}......# [ 0] : System Reset Asserted...# [ 4995000] : System Reset De-asserted...# [ 8522100] : Transaction Reset Is De-asserted...# [ 80250100] : Transaction Link Is Up...# [ 80250100] : Expected Device/Vendor ID = 425010ee# [ 80250100] : Reading from PCI/PCI-Express Configuration Register 0x00# [ 80274000] : TSK_PARSE_FRAME on Transmit# [ 81874000] : TSK_PARSE_FRAME on Receive# [ 82674000] : TEST PASSED --- Device/Vendor ID 425010ee successfully received# ** Note: $finish : ../tests/sample_tests1.v(30)# Time: 82674 ns Iteration: 11 Instance: /boardx04/xilinx_pci_exp_4_lane_downstream_port/tx_usrapp# 1# Break in Module pci_exp_usrapp_tx at ../tests/sample_tests1.v line 30quit⌨️ 快捷键说明
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