routed.twr

已经在xilinx的ML555开发板上实现的PCIEx4的设计

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1 to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_53
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y10.BQ      Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/rem_o
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1
    SLICE_X50Y26.CE      net (fanout=14)       3.259   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1
    SLICE_X50Y26.CLK     Tceck                 0.229   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o<53>
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_53
    -------------------------------------------------  ---------------------------
    Total                                      3.938ns (0.679ns logic, 3.259ns route)
                                                       (17.2% logic, 82.8% route)

--------------------------------------------------------------------------------
Slack:                  0.027ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1 (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_52 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.938ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1 to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_52
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X53Y10.BQ      Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/rem_o
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1
    SLICE_X50Y26.CE      net (fanout=14)       3.259   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1
    SLICE_X50Y26.CLK     Tceck                 0.229   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o<53>
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_52
    -------------------------------------------------  ---------------------------
    Total                                      3.938ns (0.679ns logic, 3.259ns route)
                                                       (17.2% logic, 82.8% route)

--------------------------------------------------------------------------------
Slack:                  0.028ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo (RAM)
  Requirement:          4.000ns
  Data Path Delay:      3.937ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
    Location               Delay type         Delay(ns)  Physical Resource
                                                         Logical Resource(s)
    ---------------------------------------------------  -------------------
    SLICE_X50Y7.AQ         Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.D2        net (fanout=14)       0.961   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.CMUX      Topdc                 0.389   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden2
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_f7
    RAMB36_X2Y1.ENAU       net (fanout=6)        1.723   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden
    RAMB36_X2Y1.CLKARDCLKU Trcck_RDEN            0.414   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
    ---------------------------------------------------  ---------------------------
    Total                                        3.937ns (1.253ns logic, 2.684ns route)
                                                         (31.8% logic, 68.2% route)

--------------------------------------------------------------------------------
Slack:                  0.028ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo (RAM)
  Requirement:          4.000ns
  Data Path Delay:      3.937ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
    Location               Delay type         Delay(ns)  Physical Resource
                                                         Logical Resource(s)
    ---------------------------------------------------  -------------------
    SLICE_X50Y7.AQ         Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.D2        net (fanout=14)       0.961   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.CMUX      Topdc                 0.389   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden2
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_f7
    RAMB36_X2Y1.ENARDENL   net (fanout=6)        1.723   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden
    RAMB36_X2Y1.CLKARDCLKL Trcck_RDEN            0.414   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
    ---------------------------------------------------  ---------------------------
    Total                                        3.937ns (1.253ns logic, 2.684ns route)
                                                         (31.8% logic, 68.2% route)

--------------------------------------------------------------------------------
Slack:                  0.028ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_58 (FF)
  Destination:          app/BMD/BMD_EP/EP_RX/cpld_found_o_4 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.937ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_58 to app/BMD/BMD_EP/EP_RX/cpld_found_o_4
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X43Y8.AQ       Tcko                  0.450   trn_rd_c<36>
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_58
    SLICE_X39Y6.B1       net (fanout=2)        0.990   trn_rd_c<58>
    SLICE_X39Y6.B        Tilo                  0.094   trn_rd_c<59>
                                                       app/BMD/BMD_EP/EP_RX/bmd_64_rx_state_FFd2-In311
    SLICE_X30Y5.C6       net (fanout=19)       0.638   app/BMD/BMD_EP/EP_RX/N431
    SLICE_X30Y5.C        Tilo                  0.094   app/BMD/BMD_EP/EP_RX/cpld_found_o<0>
                                                       app/BMD/BMD_EP/EP_RX/cpld_found_o_not00011
    SLICE_X25Y2.D1       net (fanout=74)       1.643   app/BMD/BMD_EP/EP_RX/cpld_found_o_not0001
    SLICE_X25Y2.CLK      Tas                   0.028   app/BMD/BMD_EP/EP_RX/cpld_found_o<4>
                                                       app/BMD/BMD_EP/EP_RX/cpld_found_o_4_rstpot
                                                       app/BMD/BMD_EP/EP_RX/cpld_found_o_4
    -------------------------------------------------  ---------------------------
    Total                                      3.937ns (0.666ns logic, 3.271ns route)
                                                       (16.9% logic, 83.1% route)

--------------------------------------------------------------------------------
Slack:                  0.029ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d (FF)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo (RAM)
  Requirement:          4.000ns
  Data Path Delay:      3.936ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/rx_fifo
    Location               Delay type         Delay(ns)  Physical Resource
                                                         Logical Resource(s)
    ---------------------------------------------------  -------------------
    SLICE_X50Y7.AQ         Tcko                  0.450   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.C2        net (fanout=14)       0.957   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_preeofout_d
    SLICE_X51Y12.CMUX      Tilo                  0.392   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_d
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden1
                                                         ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_f7
    RAMB36_X2Y1.ENAU       net (fanout=6)        1.723   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden
    RAMB36_X2Y1.CLKARDCLKU Trcck_RDEN            0.414   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_