📄 routed.twr
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Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_vld_d to app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o_5 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X43Y9.DQ Tcko 0.450 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_vld_d ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_vld_d SLICE_X29Y15.A5 net (fanout=17) 0.977 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_vld_d SLICE_X29Y15.A Tilo 0.094 app/BMD/BMD_EP/EP_RX/req_compl_o app/BMD/BMD_EP/EP_RX/cpld_malformed_o_mux000041 SLICE_X31Y9.A1 net (fanout=11) 1.355 app/BMD/BMD_EP/EP_RX/N52 SLICE_X31Y9.A Tilo 0.094 app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o<3> app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o_not00011 SLICE_X33Y13.CE net (fanout=7) 0.754 app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o_not0001 SLICE_X33Y13.CLK Tceck 0.229 app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o<5> app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o_5 ------------------------------------------------- --------------------------- Total 3.953ns (0.867ns logic, 3.086ns route) (21.9% logic, 78.1% route)--------------------------------------------------------------------------------Slack: 0.015ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.950ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- RAMB36_X1Y5.DOADOL2 Trcko_DO 0.922 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst PCIE_X0Y0.MIMDLLBRDATA4 net (fanout=1) 3.130 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_brdata<4> PCIE_X0Y0.CRMCORECLK Tpcidck_DLRETRY -0.102 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ---------------------------------------------------- --------------------------- Total 3.950ns (0.820ns logic, 3.130ns route) (20.8% logic, 79.2% route)--------------------------------------------------------------------------------Slack: 0.015ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/cpl_tlp_rcntr_p1_1 (FF) Destination: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available (FF) Requirement: 4.000ns Data Path Delay: 3.950ns (Levels of Logic = 3) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/cpl_tlp_rcntr_p1_1 to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X55Y24.BQ Tcko 0.450 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/cpl_tlp_rcntr_p1<3> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/cpl_tlp_rcntr_p1_1 SLICE_X56Y25.D1 net (fanout=2) 1.062 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/cpl_tlp_rcntr_p1<1> SLICE_X56Y25.D Tilo 0.094 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/last_completion ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_cmp_eq00008126 SLICE_X56Y25.A1 net (fanout=1) 0.743 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_cmp_eq00008_map44 SLICE_X56Y25.A Tilo 0.094 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/last_completion ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_cmp_eq00008142 SLICE_X56Y26.B4 net (fanout=2) 0.545 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_cmp_eq0000 SLICE_X56Y26.B Tilo 0.094 ep/BU2/U0/pcie_ep0/pcie_blk/SIO/.pcie_gt_wrapper_i/gt_rx_status_reg<9> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_or00001 SLICE_X58Y26.SR net (fanout=1) 0.321 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available_or0000 SLICE_X58Y26.CLK Tsrck 0.547 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/completion_available ------------------------------------------------- --------------------------- Total 3.950ns (1.279ns logic, 2.671ns route) (32.4% logic, 67.6% route)--------------------------------------------------------------------------------Slack: 0.023ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/src_rdy_o (FF) Destination: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_7 (FF) Requirement: 4.000ns Data Path Delay: 3.942ns (Levels of Logic = 3) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/src_rdy_o to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_7 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X51Y12.AQ Tcko 0.450 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_rden_d ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/src_rdy_o SLICE_X40Y22.A1 net (fanout=37) 2.063 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/src_rdy_o SLICE_X40Y22.A Tilo 0.094 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_sub0000<1> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_sub0000<1>1 SLICE_X41Y22.C1 net (fanout=12) 0.733 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_sub0000<1> SLICE_X41Y22.COUT Topcyc 0.423 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto<3> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/Madd_pcpl_addto_add0000_lut<2> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/Madd_pcpl_addto_add0000_cy<3> SLICE_X41Y23.CIN net (fanout=1) 0.000 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/Madd_pcpl_addto_add0000_cy<3> SLICE_X41Y23.CLK Tcinck 0.179 ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto<7> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/Madd_pcpl_addto_add0000_cy<7> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/pcpl_addto_7 ------------------------------------------------- --------------------------- Total 3.942ns (1.146ns logic, 2.796ns route) (29.1% logic, 70.9% route)--------------------------------------------------------------------------------Slack: 0.025ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst (RAM) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Requirement: 4.000ns Data Path Delay: 3.940ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep Location Delay type Delay(ns) Physical Resource Logical Resource(s) ---------------------------------------------------- ------------------- RAMB36_X1Y9.DOBDOU7 Trcko_DOB 0.818 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_tx/generate_tdp2[1].ram_tdp2_inst PCIE_X0Y0.MIMTXBRDATA47 net (fanout=1) 3.015 ep/BU2/U0/pcie_ep0/pcie_blk/mim_tx_brdata<47> PCIE_X0Y0.CRMCORECLK Tpcidck_TXRAM 0.107 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ---------------------------------------------------- --------------------------- Total 3.940ns (0.925ns logic, 3.015ns route) (23.5% logic, 76.5% route)--------------------------------------------------------------------------------Slack: 0.027ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/malformed_checks/sof_q1 (FF) Destination: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/snk_inst/bar_hit/check_raddr_o_53 (FF) Requirement: 4.000ns Data Path Delay: 3.938ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns⌨️ 快捷键说明
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