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SLICE_X24Y7.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<23> SLICE_X24Y7.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<27> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<27> SLICE_X24Y8.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<27> SLICE_X24Y8.AMUX Tcina 0.274 app/BMD/BMD_EP/EP_RX/cpld_found_o_addsub0000<31> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_xor<31> SLICE_X25Y7.D1 net (fanout=1) 1.024 app/BMD/BMD_EP/EP_RX/cpld_found_o_addsub0000<28> SLICE_X25Y7.CLK Tas 0.028 app/BMD/BMD_EP/EP_RX/cpld_found_o<28> app/BMD/BMD_EP/EP_RX/cpld_found_o_28_rstpot app/BMD/BMD_EP/EP_RX/cpld_found_o_28 ------------------------------------------------- --------------------------- Total 3.962ns (1.875ns logic, 2.087ns route) (47.3% logic, 52.7% route)--------------------------------------------------------------------------------Slack: 0.004ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.961ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- PCIE_X0Y0.MIMDLLBWDATA45 Tpcicko_DLRETRY 0.673 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.DIBDIU6 net (fanout=1) 2.946 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_bwdata<45> RAMB36_X1Y5.CLKBWRCLKU Trdck_DI_ECC 0.342 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ----------------------------------------------------- --------------------------- Total 3.961ns (1.015ns logic, 2.946ns route) (25.6% logic, 74.4% route)--------------------------------------------------------------------------------Slack: 0.006ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.959ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- PCIE_X0Y0.MIMDLLBWDATA13 Tpcicko_DLRETRY 0.562 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.DIADIU6 net (fanout=1) 3.055 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_bwdata<13> RAMB36_X1Y5.CLKBWRCLKU Trdck_DI_ECC 0.342 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ----------------------------------------------------- --------------------------- Total 3.959ns (0.904ns logic, 3.055ns route) (22.8% logic, 77.2% route)--------------------------------------------------------------------------------Slack: 0.007ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.958ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- PCIE_X0Y0.MIMDLLBWDATA48 Tpcicko_DLRETRY 0.659 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.DIBDIL8 net (fanout=1) 2.957 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_bwdata<48> RAMB36_X1Y5.CLKBWRCLKL Trdck_DI_ECC 0.342 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ----------------------------------------------------- --------------------------- Total 3.958ns (1.001ns logic, 2.957ns route) (25.3% logic, 74.7% route)--------------------------------------------------------------------------------Slack: 0.008ns (requirement - (data path - clock path skew + uncertainty)) Source: app/BMD/BMD_EP/EP_TX/compl_done_o (FF) Destination: app/BMD/BMD_EP/EP_TX/pmwr_addr_10 (FF) Requirement: 4.000ns Data Path Delay: 3.957ns (Levels of Logic = 3) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: app/BMD/BMD_EP/EP_TX/compl_done_o to app/BMD/BMD_EP/EP_TX/pmwr_addr_10 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X25Y29.CQ Tcko 0.450 app/BMD/BMD_EP/EP_TX/compl_done_o app/BMD/BMD_EP/EP_TX/compl_done_o SLICE_X25Y33.B3 net (fanout=14) 0.905 app/BMD/BMD_EP/EP_TX/compl_done_o SLICE_X25Y33.B Tilo 0.094 app/BMD/BMD_EP/EP_TX/trn_tsof_n_and0000 app/BMD/BMD_EP/EP_TX/trn_tsof_n_and00001 SLICE_X10Y30.B4 net (fanout=28) 1.034 app/BMD/BMD_EP/EP_TX/trn_tsof_n_and0000 SLICE_X10Y30.B Tilo 0.094 app/BMD/BMD_EP/EP_TX/cur_wr_not1st app/BMD/BMD_EP/EP_TX/pmwr_addr_mux0000<0>22 SLICE_X7Y28.A1 net (fanout=30) 1.354 app/BMD/BMD_EP/EP_TX/N331 SLICE_X7Y28.CLK Tas 0.026 app/BMD/BMD_EP/EP_TX/pmwr_addr<10> app/BMD/BMD_EP/EP_TX/pmwr_addr_mux0000<21>1 app/BMD/BMD_EP/EP_TX/pmwr_addr_10 ------------------------------------------------- --------------------------- Total 3.957ns (0.664ns logic, 3.293ns route) (16.8% logic, 83.2% route)--------------------------------------------------------------------------------Slack: 0.010ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU) Destination: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst (RAM) Requirement: 4.000ns Data Path Delay: 3.955ns (Levels of Logic = 0) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst Location Delay type Delay(ns) Physical Resource Logical Resource(s) ----------------------------------------------------- ------------------- PCIE_X0Y0.MIMDLLBWDATA59 Tpcicko_DLRETRY 0.625 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep RAMB36_X1Y5.DIBDIU13 net (fanout=1) 2.988 ep/BU2/U0/pcie_ep0/pcie_blk/mim_dll_bwdata<59> RAMB36_X1Y5.CLKBWRCLKU Trdck_DI_ECC 0.342 ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_retry/generate_sdp.ram_sdp_inst ----------------------------------------------------- --------------------------- Total 3.955ns (0.967ns logic, 2.988ns route) (24.5% logic, 75.5% route)--------------------------------------------------------------------------------Slack: 0.012ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/bram_vld_d (FF) Destination: app/BMD/BMD_EP/EP_RX/cpl_ur_tag_o_5 (FF) Requirement: 4.000ns Data Path Delay: 3.953ns (Levels of Logic = 2) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns⌨️ 快捷键说明
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