📄 routed.twr
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(26.6% logic, 73.4% route)--------------------------------------------------------------------------------Slack: 0.002ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 (FF) Destination: app/BMD/BMD_EP/EP_RX/req_tc_o_0 (FF) Requirement: 4.000ns Data Path Delay: 3.963ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 to app/BMD/BMD_EP/EP_RX/req_tc_o_0 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X42Y7.BQ Tcko 0.450 trn_rd_c<38> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 SLICE_X42Y7.D1 net (fanout=4) 0.898 trn_rd_c<41> SLICE_X42Y7.D Tilo 0.094 trn_rd_c<38> app/BMD/BMD_EP/EP_RX/req_tc_o_not0001144 SLICE_X41Y9.B6 net (fanout=1) 0.280 app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map19 SLICE_X41Y9.B Tilo 0.094 trn_rd_c<35> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011114 SLICE_X41Y9.A5 net (fanout=1) 0.224 app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map24 SLICE_X41Y9.A Tilo 0.094 trn_rd_c<35> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011219 SLICE_X29Y20.C6 net (fanout=4) 1.027 app/BMD/N162 SLICE_X29Y20.C Tilo 0.094 app/BMD/BMD_EP/EP_RX/req_tag_o<7> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011 SLICE_X31Y20.CE net (fanout=9) 0.479 app/BMD/BMD_EP/EP_RX/req_tc_o_not0001 SLICE_X31Y20.CLK Tceck 0.229 app/BMD/BMD_EP/EP_RX/req_tc_o<0> app/BMD/BMD_EP/EP_RX/req_tc_o_0 ------------------------------------------------- --------------------------- Total 3.963ns (1.055ns logic, 2.908ns route) (26.6% logic, 73.4% route)--------------------------------------------------------------------------------Slack: 0.002ns (requirement - (data path - clock path skew + uncertainty)) Source: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 (FF) Destination: app/BMD/BMD_EP/EP_RX/req_rid_o_8 (FF) Requirement: 4.000ns Data Path Delay: 3.963ns (Levels of Logic = 4) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 to app/BMD/BMD_EP/EP_RX/req_rid_o_8 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X42Y7.BQ Tcko 0.450 trn_rd_c<38> ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 SLICE_X42Y7.D1 net (fanout=4) 0.898 trn_rd_c<41> SLICE_X42Y7.D Tilo 0.094 trn_rd_c<38> app/BMD/BMD_EP/EP_RX/req_tc_o_not0001144 SLICE_X41Y9.B6 net (fanout=1) 0.280 app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map19 SLICE_X41Y9.B Tilo 0.094 trn_rd_c<35> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011114 SLICE_X41Y9.A5 net (fanout=1) 0.224 app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map24 SLICE_X41Y9.A Tilo 0.094 trn_rd_c<35> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011219 SLICE_X29Y20.C6 net (fanout=4) 1.027 app/BMD/N162 SLICE_X29Y20.C Tilo 0.094 app/BMD/BMD_EP/EP_RX/req_tag_o<7> app/BMD/BMD_EP/EP_RX/req_tc_o_not00011 SLICE_X31Y20.CE net (fanout=9) 0.479 app/BMD/BMD_EP/EP_RX/req_tc_o_not0001 SLICE_X31Y20.CLK Tceck 0.229 app/BMD/BMD_EP/EP_RX/req_tc_o<0> app/BMD/BMD_EP/EP_RX/req_rid_o_8 ------------------------------------------------- --------------------------- Total 3.963ns (1.055ns logic, 2.908ns route) (26.6% logic, 73.4% route)--------------------------------------------------------------------------------Slack: 0.003ns (requirement - (data path - clock path skew + uncertainty)) Source: app/BMD/BMD_EP/EP_TX/pmwr_addr_3 (FF) Destination: app/BMD/BMD_EP/EP_TX/pmwr_addr_27 (FF) Requirement: 4.000ns Data Path Delay: 3.962ns (Levels of Logic = 8) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: app/BMD/BMD_EP/EP_TX/pmwr_addr_3 to app/BMD/BMD_EP/EP_TX/pmwr_addr_27 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X10Y26.BQ Tcko 0.471 app/BMD/BMD_EP/EP_TX/mwr_len_byte<2> app/BMD/BMD_EP/EP_TX/pmwr_addr_3 SLICE_X6Y26.BX net (fanout=4) 1.118 app/BMD/BMD_EP/EP_TX/pmwr_addr<3> SLICE_X6Y26.COUT Tbxcy 0.346 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<5> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<5> SLICE_X6Y27.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<5> SLICE_X6Y27.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<9> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<9> SLICE_X6Y28.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<9> SLICE_X6Y28.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<13> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<13> SLICE_X6Y29.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<13> SLICE_X6Y29.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<17> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<17> SLICE_X6Y30.CIN net (fanout=1) 0.010 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<17> SLICE_X6Y30.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<21> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<21> SLICE_X6Y31.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<21> SLICE_X6Y31.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<25> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<25> SLICE_X6Y32.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<25> SLICE_X6Y32.BMUX Tcinb 0.335 app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<29> app/BMD/BMD_EP/EP_TX/Madd_pmwr_addr_addsub0000_cy<29> SLICE_X10Y32.A1 net (fanout=1) 1.155 app/BMD/BMD_EP/EP_TX/pmwr_addr_addsub0000<27> SLICE_X10Y32.CLK Tas 0.007 app/BMD/BMD_EP/EP_TX/pmwr_addr<27> app/BMD/BMD_EP/EP_TX/pmwr_addr_mux0000<4>1 app/BMD/BMD_EP/EP_TX/pmwr_addr_27 ------------------------------------------------- --------------------------- Total 3.962ns (1.679ns logic, 2.283ns route) (42.4% logic, 57.6% route)--------------------------------------------------------------------------------Slack: 0.003ns (requirement - (data path - clock path skew + uncertainty)) Source: app/BMD/BMD_EP/EP_RX/cpld_found_o_0 (FF) Destination: app/BMD/BMD_EP/EP_RX/cpld_found_o_28 (FF) Requirement: 4.000ns Data Path Delay: 3.962ns (Levels of Logic = 9) Clock Path Skew: 0.000ns Source Clock: trn_clk_c rising at 0.000ns Destination Clock: trn_clk_c rising at 4.000ns Clock Uncertainty: 0.035ns Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.070ns Total Input Jitter (TIJ): 0.000ns Discrete Jitter (DJ): 0.000ns Phase Error (PE): 0.000ns Maximum Data Path: app/BMD/BMD_EP/EP_RX/cpld_found_o_0 to app/BMD/BMD_EP/EP_RX/cpld_found_o_28 Location Delay type Delay(ns) Physical Resource Logical Resource(s) ------------------------------------------------- ------------------- SLICE_X30Y5.BQ Tcko 0.450 app/BMD/BMD_EP/EP_RX/cpld_found_o<0> app/BMD/BMD_EP/EP_RX/cpld_found_o_0 SLICE_X24Y1.A5 net (fanout=4) 1.063 app/BMD/BMD_EP/EP_RX/cpld_found_o<0> SLICE_X24Y1.COUT Topcya 0.499 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<3> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_lut<0>_INV_0 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<3> SLICE_X24Y2.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<3> SLICE_X24Y2.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<7> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<7> SLICE_X24Y3.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<7> SLICE_X24Y3.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<11> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<11> SLICE_X24Y4.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<11> SLICE_X24Y4.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<15> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<15> SLICE_X24Y5.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<15> SLICE_X24Y5.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<19> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<19> SLICE_X24Y6.CIN net (fanout=1) 0.000 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<19> SLICE_X24Y6.COUT Tbyp 0.104 app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<23> app/BMD/BMD_EP/EP_RX/Madd_cpld_found_o_addsub0000_cy<23>⌨️ 快捷键说明
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