routed.twr

已经在xilinx的ML555开发板上实现的PCIEx4的设计

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Release 9.2.03i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

trce -u -v 100 routed.ncd mapped.pcf

Design file:              routed.ncd
Physical constraint file: mapped.pcf
Device,package,speed:     xc5vlx50t,ff1136,-1 (PRODUCTION 1.57 2007-08-28, STEPPING level 0)
Report level:             verbose report, limited to 100 items per constraint
                          unconstrained path report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: NET "sys_clk_c" PERIOD = 10 ns HIGH 50%;

 0 items analyzed, 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: PERIOD analysis for net 
"ep/BU2/U0/pcie_ep0/pcie_blk/clocking_i/clkout0" derived from  NET "sys_clk_c" 
PERIOD = 10 ns HIGH 50%;  divided by 2.50  to 4 nS   

 43878 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
 Minimum period is   4.000ns.
--------------------------------------------------------------------------------
Slack:                  0.000ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/posted_avail (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.965ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep to ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/posted_avail
    Location                   Delay type         Delay(ns)  Physical Resource
                                                             Logical Resource(s)
    -------------------------------------------------------  -------------------
    PCIE_X0Y0.LLKRXSRCLASTREQN Tpcicko_LLK           1.417   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                             ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    SLICE_X57Y22.A2            net (fanout=15)       1.408   ep/BU2/U0/pcie_ep0/llk_rx_src_last_req_n
    SLICE_X57Y22.A             Tilo                  0.094   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/any_available_d
                                                             ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/trigger_xfer1
    SLICE_X59Y18.CE            net (fanout=7)        0.817   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/trigger_xfer
    SLICE_X59Y18.CLK           Tceck                 0.229   ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/posted_avail
                                                             ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/arb_inst/posted_avail
    -------------------------------------------------------  ---------------------------
    Total                                            3.965ns (1.740ns logic, 2.225ns route)
                                                             (43.9% logic, 56.1% route)

--------------------------------------------------------------------------------
Slack:                  0.001ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst (RAM)
  Destination:          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep (CPU)
  Requirement:          4.000ns
  Data Path Delay:      3.964ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst to ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    Location                Delay type         Delay(ns)  Physical Resource
                                                          Logical Resource(s)
    ----------------------------------------------------  -------------------
    RAMB36_X1Y8.DOBDOL9     Trcko_DOB             0.818   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_mim_wrapper_i/bram_tl_rx/generate_tdp2[1].ram_tdp2_inst
    PCIE_X0Y0.MIMRXBRDATA50 net (fanout=1)        2.967   ep/BU2/U0/pcie_ep0/pcie_blk/mim_rx_brdata<50>
    PCIE_X0Y0.CRMCORECLK    Tpcidck_RXRAM         0.179   ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
                                                          ep/BU2/U0/pcie_ep0/pcie_blk/pcie_ep
    ----------------------------------------------------  ---------------------------
    Total                                         3.964ns (0.997ns logic, 2.967ns route)
                                                          (25.2% logic, 74.8% route)

--------------------------------------------------------------------------------
Slack:                  0.002ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 (FF)
  Destination:          app/BMD/BMD_EP/EP_RX/req_rid_o_11 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.963ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 to app/BMD/BMD_EP/EP_RX/req_rid_o_11
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y7.BQ       Tcko                  0.450   trn_rd_c<38>
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41
    SLICE_X42Y7.D1       net (fanout=4)        0.898   trn_rd_c<41>
    SLICE_X42Y7.D        Tilo                  0.094   trn_rd_c<38>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not0001144
    SLICE_X41Y9.B6       net (fanout=1)        0.280   app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map19
    SLICE_X41Y9.B        Tilo                  0.094   trn_rd_c<35>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011114
    SLICE_X41Y9.A5       net (fanout=1)        0.224   app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map24
    SLICE_X41Y9.A        Tilo                  0.094   trn_rd_c<35>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011219
    SLICE_X29Y20.C6      net (fanout=4)        1.027   app/BMD/N162
    SLICE_X29Y20.C       Tilo                  0.094   app/BMD/BMD_EP/EP_RX/req_tag_o<7>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011
    SLICE_X31Y20.CE      net (fanout=9)        0.479   app/BMD/BMD_EP/EP_RX/req_tc_o_not0001
    SLICE_X31Y20.CLK     Tceck                 0.229   app/BMD/BMD_EP/EP_RX/req_tc_o<0>
                                                       app/BMD/BMD_EP/EP_RX/req_rid_o_11
    -------------------------------------------------  ---------------------------
    Total                                      3.963ns (1.055ns logic, 2.908ns route)
                                                       (26.6% logic, 73.4% route)

--------------------------------------------------------------------------------
Slack:                  0.002ns (requirement - (data path - clock path skew + uncertainty))
  Source:               ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 (FF)
  Destination:          app/BMD/BMD_EP/EP_RX/req_tag_o_0 (FF)
  Requirement:          4.000ns
  Data Path Delay:      3.963ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         trn_clk_c rising at 0.000ns
  Destination Clock:    trn_clk_c rising at 4.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path: ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41 to app/BMD/BMD_EP/EP_RX/req_tag_o_0
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X42Y7.BQ       Tcko                  0.450   trn_rd_c<38>
                                                       ep/BU2/U0/pcie_ep0/pcie_blk_if/ll_bridge/rx_bridge/fifo_inst/trn_rd_41
    SLICE_X42Y7.D1       net (fanout=4)        0.898   trn_rd_c<41>
    SLICE_X42Y7.D        Tilo                  0.094   trn_rd_c<38>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not0001144
    SLICE_X41Y9.B6       net (fanout=1)        0.280   app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map19
    SLICE_X41Y9.B        Tilo                  0.094   trn_rd_c<35>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011114
    SLICE_X41Y9.A5       net (fanout=1)        0.224   app/BMD/BMD_EP/EP_RX/req_tc_o_not00011_map24
    SLICE_X41Y9.A        Tilo                  0.094   trn_rd_c<35>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011219
    SLICE_X29Y20.C6      net (fanout=4)        1.027   app/BMD/N162
    SLICE_X29Y20.C       Tilo                  0.094   app/BMD/BMD_EP/EP_RX/req_tag_o<7>
                                                       app/BMD/BMD_EP/EP_RX/req_tc_o_not00011
    SLICE_X31Y20.CE      net (fanout=9)        0.479   app/BMD/BMD_EP/EP_RX/req_tc_o_not0001
    SLICE_X31Y20.CLK     Tceck                 0.229   app/BMD/BMD_EP/EP_RX/req_tc_o<0>
                                                       app/BMD/BMD_EP/EP_RX/req_tag_o_0
    -------------------------------------------------  ---------------------------
    Total                                      3.963ns (1.055ns logic, 2.908ns route)