📄 start.asm
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#set CONFIG_STAMP OFF ; <<< enable bit pattern with
; current configuration at end of
; start module (a few bytes)
#if VERSION_STAMP == ON
.SECTION VERSIONS, CONST ; change name, if necessary
.SDATA "Start ", VERSION, "\n\0"
#endif
; <<< END OF SETTINGS >>>
;====================================================================
; 5 Section and Data Declaration
;====================================================================
;====================================================================
; 5.1 Several fixed addresses (fixed for MB90xxx controllers)
;====================================================================
LPMCR .EQU 0xA0 ; Low power mode control register
CKSCR .EQU 0xA1 ; Clock select control register
#if BUSMODE != SINGLE_CHIP
ARSR .EQU 0xA5 ; *1) Automatic ready function reg
HACR .EQU 0xA6 ; *1) External address output reg
EPCR .EQU 0xA7 ; *1) Bus control signal selection
#endif
#if FAMILY == MB90500 || FAMILY == MB90400 || FAMILY == MB90300 || FAMILY == MB90800 || FAMILY == MB90900
ROMM .EQU 0x6F ; *2) ROM mirror control register
#endif
WDTC .EQU 0xA8 ; Watchdog control register
TBTC .EQU 0xA9 ; Timerbase timer control register
; *1 only for devices with external bus
; *2 only for MB905xx (FFMC-16LX) devices
;====================================================================
; 5.2 Declaration of __near addressed data sections
;====================================================================
; sections to be cleared
.SECTION DATA, DATA, ALIGN=2 ; zero clear area
.SECTION DATA2, DATA, ALIGN=2 ; zero clear area
.SECTION DIRDATA, DIR, ALIGN=2 ; zero clear direct
.SECTION LIBDATA, DATA, ALIGN=2 ; zero clear lib area
; sections to be initialised with start-up values
.SECTION INIT, DATA, ALIGN=2 ; initialised area
.SECTION INIT2, DATA, ALIGN=2 ; initialised area
.SECTION DIRINIT, DIR, ALIGN=2 ; initialised dir
.SECTION LIBINIT, DATA, ALIGN=2 ; initialised lib area
#if CONSTDATA == RAMCONST
.SECTION CINIT, DATA, ALIGN=2 ; initialised const
.SECTION CINIT2, DATA, ALIGN=2 ; initialised const
#endif
; sections containing start-up values for initialised sections above
.SECTION DCONST, CONST, ALIGN=2 ; DINIT initialisers
.SECTION DIRCONST, DIRCONST,ALIGN=2 ; DIRINIT initialisers
.SECTION LIBDCONST, CONST, ALIGN=2 ; LIBDCONST init val
; following setion is either copied to CINIT (RAMCONST) or
; mapped by ROM-mirror function (ROMCONST)
.SECTION CONST, CONST, ALIGN=2 ; CINIT initialisers
.SECTION CONST2, CONST, ALIGN=2 ; CINIT initialisers
;====================================================================
; 5.3 Declaration of RAMCODE section and labels
;====================================================================
#if COPY_RAMCODE == ON
.SECTION RAMCODE, CODE, ALIGN=1
.IMPORT _RAM_RAMCODE ; provided by linker
.IMPORT _ROM_RAMCODE ; provided by linker
#endif
;====================================================================
; 5.4 Declaration of sections containing other sections description
;====================================================================
; DCLEAR contains start address and size of all sections to be cleared
; DTRANS contains source and destination address and size of all
; sections to be initialised with start-up values
; The compiler automatically adds a descriptor for each __far addressed
; data section to DCLEAR or DTRANS. These __far section are separated
; for each C-module.
; In addition the start-up file adds the descriptors of the previously
; declared __near section here. This way the same code in the start-up
; file can be used for initialising all sections.
.SECTION DCLEAR, CONST, ALIGN=2 ; zero clear table
; Address Bank Size
.DATA.H DATA, BNKSEC DATA, SIZEOF(DATA )
.DATA.H DIRDATA, BNKSEC DIRDATA, SIZEOF(DIRDATA)
.DATA.H LIBDATA, BNKSEC LIBDATA, SIZEOF(LIBDATA)
.SECTION DTRANS, CONST, ALIGN=2 ; copy table
; Address Bank Address Bank Size
.DATA.H DCONST, BNKSEC DCONST, INIT, BNKSEC INIT, SIZEOF INIT
.DATA.H DIRCONST, BNKSEC DIRCONST, DIRINIT,BNKSEC DIRINIT,SIZEOF DIRINIT
.DATA.H LIBDCONST,BNKSEC LIBDCONST,LIBINIT,BNKSEC LIBINIT,SIZEOF LIBINIT
#if CONSTDATA == RAMCONST
.DATA.H CONST, BNKSEC CONST, CINIT, BNKSEC CINIT, SIZEOF CINIT
.DATA.H CONST2, BNKSEC CONST, CINIT2, BNKSEC CINIT2, SIZEOF CINIT2
#endif
#if COPY_RAMCODE == ON
.DATA.L _ROM_RAMCODE, _RAM_RAMCODE
.DATA.H SIZEOF RAMCODE
#endif
;====================================================================
; 5.5 Stack area and stack top definition/declaration
;====================================================================
#if STACK_RESERVE == ON
.SECTION SSTACK, STACK, ALIGN=2
.EXPORT __systemstack, __systemstack_top
__systemstack:
.RES.B (STACK_SYS_SIZE + 1) & 0xFFFE
__systemstack_top:
SSTACK_TOP:
.SECTION USTACK, STACK, ALIGN=2
.EXPORT __userstack, __userstack_top
__userstack:
.RES.B (STACK_USR_SIZE + 1) & 0xFFFE
__userstack_top:
USTACK_TOP:
#else
.SECTION SSTACK, STACK, ALIGN=2
.SECTION USTACK, STACK, ALIGN=2
.IMPORT __systemstack, __systemstack_top
.IMPORT __userstack, __userstack_top
#endif
;====================================================================
; 5.6 Direct page register dummy label definition
;====================================================================
.SECTION DIRDATA ; zero clear direct
DIRDATA_S: ; label for DPR init
; This label is used to get the page of the __direct data.
; Depending on the linkage order order this startup file the label is
; placed anywhere within the __direct data page. However, the
; statement "PAGE (DIRDATA_S)" is processed. Therefore, the lower
; 8 Bit of the address of DIRDATA_S are not relevant and this feature
; becomes linkage order independent.
; Note, the linker settings have to make sure that the all __direct
; data are located within the same physical page (256 Byte block).
;====================================================================
; 6 Start-Up Code
;====================================================================
;====================================================================
; 6.1 Import external symbols
;====================================================================
.IMPORT _main ; user code entrance
#if CLIBINIT == ON
.IMPORT __stream_init
.IMPORT _exit
.EXPORT __exit
#endif
.EXPORT _start
;====================================================================
; ___ _____ __ ___ _____
; / | / \ | \ |
; \___ | | | |___/ |
; \ | |----| | \ |
; ___/ | | | | \ | Begin of actual code section
;====================================================================
.SECTION CODE_START, CODE, ALIGN=1
;====================================================================
; 6.2 Program start (the reset vector should point here)
;====================================================================
_start:
NOP ; This NOP is only for debugging. On debugger the IP
; (instruction pointer) should point here after reset
;====================================================================
; 6.3 "NOT RESET YET" WARNING
;====================================================================
notresetyet:
NOP ; read hint below!!!!!!!
; If the debugger stays at this NOP after download, the controller has
; not been reset yet. In order to reset all hardware register it is
; highly recommended to reset the controller.
; However, if no reset vector has been defined on purpose, this start
; address can also be used.
; This mechanism is using the .END instruction at the end of this mo-
; dule. It is not necessary for controller operation but improves
; security during debugging (mainly emulator debugger).
; If the debugger stays here after a single step from label "_start"
; to label "notresetyet", this note can be ignored.
;====================================================================
; 6.4 Initialisation of processor status
;====================================================================
AND CCR, #0 ; disable interrups
MOV ILM,#7 ; set interrupt level mask to ALL
MOV RP,#REGBANK ; set register bank pointer
;====================================================================
; 6.5 Set clock ratio (ignore subclock)
;====================================================================
#if CLOCKSPEED != NOCLOCK
SETB I:CKSCR:2 ; set main clock
# if CLOCKSPEED > MAINCLOCK
NOP ; ensure that PLL is stopped before
NOP ; writing to CKSCR and PSCCR, the
NOP ; instructions after NOP and before
NOP ; writing CKSCR/PSCCR do not give
; enough cycles (n = f_pll/f_main)
MOV A, I:CKSCR ; copy clock register
AND A, #0xFC ; set x1 for PLL
# if CLOCKSPEED == PLLx2
OR A, #0x01 ; set x2 for PLL
# elif CLOCKSPEED == PLLx3 || CLOCKSPEED == PLLx6
OR A, #0x02 ; set x3 for PLL
# elif CLOCKSPEED == PLLx4 || CLOCKSPEED == PLLx8
OR A, #0x03 ; set x4 for PLL
# endif
MOV I:CKSCR, A ; write back
#if EXTENDED_PLL == ON
MOVN A, #0 ; set bank 0 for PSCCR, for the case that
MOV DTB, A ; start-up code was not jumped by reset
# if CLOCKSPEED == PLLx6 || CLOCKSPEED == PLLx8
MOV PSCCR, #0x01 ; double the factor
# else
MOV PSCCR, #0x00 ; no doubling
# endif ; CLOCKSPEED
#endif ; EXTENDED_PLL
CLRB I:CKSCR:2 ; enable PLL, PLL is not switched
; to the MCU yet but after stabi-
; lizing it switchs on its own to
; higher speed (see below)
# endif ; CLOCKSPEED > MAINCLOCK
#endif ; CLOCKSPEED != NOCLOCK
;====================================================================
; 6.6 Set external bus configuaration
;====================================================================
#if BUSMODE != SINGLE_CHIP ; ext bus used
MOV I:HACR, #ADDR_PINS ; set used upper address lines
MOV I:EPCR, #BUS_SIGNAL ; set used bus signals
MOV I:ARSR, #iARSR ; set auto-wait cycles
#endif
#if FAMILY == MB90500 || FAMILY == MB90400 || FAMILY == MB90300 || FAMILY == MB90800 || FAMILY == MB90900
; only these have ROMM
# if BUSMODE == INTROM_EXTBUS ; EXTBUS and INTROM/EXTROM
# if ROMMIRROR == OFF && CONSTDATA == ROMCONST
# error Mirror function must be ON to mirror internal ROM
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