📄 mb90350.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.26 */
/* Id: mb90350.asm,v 1.4 2006/12/27 10:18:01 hwech Exp */
/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
/* ELIGIBILITY FOR ANY PURPOSES. */
/* (C) Fujitsu Microelectronics Europe GmbH */
/* ***************************************************************************** */
/* Fujitsu Microelectronics Europe GmbH */
/* http://emea.fujitsu.com/microelectronics */
/* */
/* The following software is for demonstration purposes only. It is not */
/* fully tested, nor validated in order to fullfill its task under all */
/* circumstances. Therefore, this software or any part of it must only be */
/* used in an evaluation laboratory environment. */
/* This software is subject to the rules of our standard DISCLAIMER, that is */
/* delivered with our SW-tools on the Fujitsu Microcontrollers CD */
/* (V3.4 or higher "\START.HTM") or on our Internet Pages: */
/* http://www.fme.gsdc.de/gsdc.htm */
/* http://emea.fujitsu.com/microelectronics */
/* ***************************************************************************** */
/* */
/* NOTE: */
/* */
/* This header-file will cover all features of the EMB90350series. */
/* Not all versions of the MB90350series may support all features ! */
/* Please DO NOT USE resources / registers others than specified */
/* for the dedicated Flash-/Mask-version. */
/* Please refer to the datasheet and hardwaremanual of the MB90350series. */
/* */
/* */
/* ---------------------------------------------------------------------- */
/* Id: mb90350.iow,v 1.5 2006/12/27 10:16:42 hwech Exp */
/* ---------------------------------------------------------------------- */
/* History: */
/* Date Version Author Description */
/* Id: mb90350.iow,v 1.1 2003/10/01 08:51:48 dfisch Exp */
/* - created (from MB90340.iow v4.4), based on MB90350_info_0.8 */
/* Id: mb90350.iow,v 1.2 2004/03/11 08:48:45 dfisch Exp */
/* bugfix for version 1.1 (based MB90340.iow v4.5) */
/* modifications based on MB90350:DS07-13737-1E */
/* - PPG0/1/2/3 deleted */
/* - PPGC5/7 added, PPGCS45/67 corrected, PRL0/2 added */
/* - Register CSVCR, CSVTR deleted */
/* - I2C ch1 deleted */
/* - Register CMCR added */
/* - ECCR3 Bitdefinitions deleted */
/* Id: mb90350.iow,v 1.3 2004/04/01 07:36:02 hwech Exp */
/* - ECCR2 Bitdefinitions deleted */
/* Id: mb90350.iow,v 1.4 2005/03/10 14:19:09 mwilla Exp */
/* - Bit definitions in PACSR0/1 corrected */
/* Id: mb90350.iow,v 1.5 2006/12/27 10:16:42 hwech Exp */
/* - Headerfiles MB90350 and MB90355 merged to MB90350 */
/* - CSVCR : Clock Supervisor added (only some devices) */
/* - FWRx : Dual Operation Flash supported (only some devices) */
/* */
/* ---------------------------------------------------------------------- */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 22.10.2002 : HWe, original version */
/* Version 1.1 15.01.2003 : HWe, ADCS0: Bit0 (STBY) deleted */
/* Id: adc_01_new.h,v 2.0 2003/05/06 09:00:19 dfisch Exp */
/* - CVS and make controlled */
/* Id: adc_01_new.h,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* Id: adc_01_new.h,v 2.2 2003/08/19 09:46:21 dfisch Exp */
/* - ADCS0 Bit-defs as const, only Byte-write */
/* ---------------------------------------------------------------------- */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* CANIO: control structures of CAN for LX-controllers */
/* */
/* Version: 1.0 23.01.99 HL */
/* - original version */
/* Version: 2.0 26.02.99 HL */
/* - unsigned int replace by IO_WORD (FR/LX have diff int) */
/* - unsigned char replace by IO_BYTE */
/* Version: 2.1 26.08.02 HLo */
/* - const specifier used for RTEC union */
/* - REC and TEC of RTEC changed from bit group to Byte type */
/* - short type addded to DTR register for compatibility */
/* Id: CANSTR.H,v 3.0 2003/05/06 09:02:30 dfisch Exp */
/* - CVS and make controlled */
/* Id: CANSTR.H,v 3.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* */
/* DESCRIPTION: Interrupt Control Register Declaration */
/* */
/* AUTHOR: Fujitsu Mikroelektronik GmbH */
/* */
/* HISTORY: */
/* Version 1.0 26.01.99: */
/* - original version */
/* Version 1.2 11.02.99 */
/* - "extern" changed to pre-defined macro of IO-Wizard */
/* (__IO_EXTERN), requires IO-Wizard 1.7 or later */
/* */
/* Version 1.3 17.07.2002 HW Bitdefinitions as const, no RMV allowed */
/* Id: ICR.H,v 2.0 2003/05/06 09:03:53 dfisch Exp */
/* - CVS and make controlled */
/* Id: ICR.H,v 2.1 2003/06/27 14:30:51 dfisch Exp */
/* - adapted to BITFIELD_ORDER_MSB */
/* ---------------------------------------------------------------------- */
/* Id: canmac1.h,v 1.1 2004/04/01 07:32:55 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* CANIO: control structures for LX-controllers */
/* version 1.0 to 2.2 for double CAN */
/* */
/* Version: 1.0 23.01.99 FMG, HLO */
/* - original version */
/* Version: 1.1 27.01.99 FMG, tka */
/* - idrx0 changed to IDRX0 */
/* Version: 1.2 11.02.99 FMG, HLO */
/* - "extern" declaration changed to predefined macros of */
/* IO-Wizard, requires IO-Wizard 1.7 or later */
/* - DRT1_LWPTR changed to DTR1_DWPTR macro */
/* Version: 2.0 28.05.01 HLO */
/* - LX-version adopted to FR */
/* - __IO_EXTENDED changed to __IO_EXTERN, CAN is on external bus */
/* Version: 2.1 08.06.01 HLO */
/* - macro for short type in DTR added */
/* Version: 2.2 11.06.01 MEN */
/* - DLC changed to IO_WORD */
/* Version: 3.0 05.08.02 DF */
/* - removed CAN1 */
/* Version: 3.1 23.08.02 DF */
/* - DTR_LWPTR and DTR_DWPTR for compatibility */
/* Version: 4.0 23.08.02 HLO */
/* - changed to batch generation */
/* Id: canmac1.h,v 1.1 2004/04/01 07:32:55 dfisch Exp */
/* - CVS and make controlled */
/* ---------------------------------------------------------------------- */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp */
/* ---------------------------------------------------------------------- */
/* Id: security.asm,v 1.1 2003/08/19 10:25:24 dfisch Exp */
/* - initial */
.PROGRAM MB90350
.TITLE MB90350
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __ader5, __ader6, __ilsr, __ilsr0, __ilsr1
.GLOBAL __ddr0, __ddr1, __ddr2, __ddr3, __ddr4, __ddr5
.GLOBAL __ddr6, __ddra, __pucr0, __pucr1, __pucr2, __pucr3
.GLOBAL __ppgc45, __ppgc4, __ppgc5, __ppgcs45, __pacsr1, __ppgc67
.GLOBAL __ppgc6, __ppgc7, __ppgcs67, __ppgc89, __ppgc8, __ppgc9
.GLOBAL __ppgcs89, __ppgcab, __ppgca, __ppgcb, __ppgcsab, __ppgccd
.GLOBAL __ppgcc, __ppgcd, __ppgcscd, __ppgcef, __ppgce, __ppgcf
.GLOBAL __ppgcsef, __ics01, __ice01, __ics45, __ice45, __ics67
.GLOBAL __ice67, __ocs45, __ocs4, __ocs5, __ocs67, __ocs6
.GLOBAL __ocs7, __tmcsr0, __tmcsr1, __tmcsr2, __tmcsr3, __adcs
.GLOBAL __adcs0, __adcs1, __adcr, __adcr0, __adcr1, __adsr
.GLOBAL __romm, __canl1, __dcsr, __dsr, __dsrl, __dsrh
.GLOBAL __pacsr0, __dirr, __lpmcr, __ckscr, __dssr, __dssr1
.GLOBAL __dssr0, __arsr, __hacr, __ecsr, __wdtc, __tbtc
.GLOBAL __wtc, __der, __derl, __derh, __fmcs, __icr
.GLOBAL __enir1, __eirr1, __elvr1, __eissr, __psccr, __bapl
.GLOBAL __bapm, __baph, __dmacs, __ioa, __ioal, __ioah
.GLOBAL __dct, __dctl, __dcth, __smr2, __scr2, __rdr2
.GLOBAL __tdr2, __ssr2, __eccr2, __escr2, __bgr2, __bgr20
.GLOBAL __bgr21
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
.org 0x000B
__ader5 .res.b 1 ;00000B
ADER5 .equ 0x000B
__ader6 .res.b 1 ;00000C
ADER6 .equ 0x000C
.org 0x000E
__ilsr .res.b 2 ;00000E
ILSR .equ 0x000E
.org 0x000E
__ilsr0 .res.b 1 ;00000E
ILSR0 .equ 0x000E
__ilsr1 .res.b 1 ;00000F
ILSR1 .equ 0x000F
__ddr0 .res.b 1 ;000010 /* PORT DIRECTION */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
.org 0x001A
__ddra .res.b 1 ;00001A
DDRA .equ 0x001A
.org 0x001C
__pucr0 .res.b 1 ;00001C /* PULL-UP CONTROL */
PUCR0 .equ 0x001C
__pucr1 .res.b 1 ;00001D
PUCR1 .equ 0x001D
__pucr2 .res.b 1 ;00001E
PUCR2 .equ 0x001E
__pucr3 .res.b 1 ;00001F
PUCR3 .equ 0x001F
.org 0x0038
__ppgc45 .res.b 2 ;000038 /* PPG control */
PPGC45 .equ 0x0038
.org 0x0038
__ppgc4 .res.b 1 ;000038
PPGC4 .equ 0x0038
__ppgc5 .res.b 1 ;000039
PPGC5 .equ 0x0039
__ppgcs45 .res.b 1 ;00003A
PPGCS45 .equ 0x003A
__pacsr1 .res.b 1 ;00003B /* Rom Correction 1 */
PACSR1 .equ 0x003B
__ppgc67 .res.b 2 ;00003C
PPGC67 .equ 0x003C
.org 0x003C
__ppgc6 .res.b 1 ;00003C
PPGC6 .equ 0x003C
__ppgc7 .res.b 1 ;00003D
PPGC7 .equ 0x003D
__ppgcs67 .res.b 1 ;00003E
PPGCS67 .equ 0x003E
.org 0x0040
__ppgc89 .res.b 2 ;000040
PPGC89 .equ 0x0040
.org 0x0040
__ppgc8 .res.b 1 ;000040
PPGC8 .equ 0x0040
__ppgc9 .res.b 1 ;000041
PPGC9 .equ 0x0041
__ppgcs89 .res.b 1 ;000042
PPGCS89 .equ 0x0042
.org 0x0044
__ppgcab .res.b 2 ;000044
PPGCAB .equ 0x0044
.org 0x0044
__ppgca .res.b 1 ;000044
PPGCA .equ 0x0044
__ppgcb .res.b 1 ;000045
PPGCB .equ 0x0045
__ppgcsab .res.b 1 ;000046
PPGCSAB .equ 0x0046
.org 0x0048
__ppgccd .res.b 2 ;000048
PPGCCD .equ 0x0048
.org 0x0048
__ppgcc .res.b 1 ;000048
PPGCC .equ 0x0048
__ppgcd .res.b 1 ;000049
PPGCD .equ 0x0049
__ppgcscd .res.b 1 ;00004A
PPGCSCD .equ 0x004A
.org 0x004C
__ppgcef .res.b 2 ;00004C
PPGCEF .equ 0x004C
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