start.lst

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                                          404      #set      PLLx2          3         ; set PLL to
                                                   x2 ext. clock/quartz
                                          405      #set      PLLx3          4         ; set PLL to
                                                   x3 ext. clock/quartz
                                          406      #set      PLLx4          5         ; set PLL to
                                                   x4 ext. clock/quartz
                                          407
                                          408      ; next factors are for specific MCU only
                                          409      ; Check datasheet or header file for presence of
                                                    register PSCCR. The
                                          410      ; header file (assembler part) must be member in
                                                    project, so linker
                                          411      ; can find the extended PLL register.
                                          412      #set      PLLx6          6         ; set PLL to
                                                   x6 ext. clock/quartz
                                          413      #set      PLLx8          7         ; set PLL to
                                                   x8 ext. clock/quartz
                                          414
                                          415
                                          416      #set      CLOCKSPEED    PLLx4      ; <<< set PLL
                                                    ratio
                                          417      #set      CLOCKWAIT      ON        ; <<< wait fo
                                                   r stabilized PLL, if
                                          418                                         ;     PLL is
                                                   used
                                          419      #set      EXTENDED_PLL   ON       ; <<< set ON,
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F2MC-16 Family SOFTUNE Assembler V30L11       2008-01-06 16:22:06   Page:  13
STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

                                                   if PSCCR exists
                                          420
                                          421      ; The clock is set quiet early. However, if CLOC
                                                   KWAIT is ON, polling
                                          422      ; for machine clock to be switched to PLL is don
                                                   e at the end of this
                                          423      ; file. Therefore, the stabilization time is not
                                                    wasted. Main() will
                                          424      ; finally start at correct speed. Resources can
                                                   immediately be used.
                                          425      ;
                                          426      ; This startup file version does not support sub
                                                   clock.
                                          427      ; Note, for controllers with extended PLL and su
                                                   b-clock the sub-clock
                                          428      ; divider is set to 4.
                                          429
                                          430      #if EXTENDED_PLL == ON
                                          431      #  define PSCCR __psccr
                                          432                .import PSCCR            ; import defi
                                                   nition from IO-file
                                          433      #else
                                          434   X
                                          435   X  #  if CLOCKSPEED > PLLx4
                                          436   X  #    error: clock > factor 4 requires spec. MCU
                                                   and EXTENDED__PLL == ON
                                          437   X  #  endif
                                          438   X
                                          439      #endif
                                          440
                                          441      ;===============================================
                                                   =====================
                                          442      ; 4.9  External Bus Interface
                                          443      ;===============================================
                                                   =====================
                                          444
                                          445      #set      SINGLE_CHIP    0         ; all interna
                                                   l
                                          446      #set      INTROM_EXTBUS  1         ; mask ROM, F
                                                   LASH, or OTP ROM used
                                          447      #set      EXTROM_EXTBUS  2         ; full extern
                                                   al bus (INROM not used)
                                          448
                                          449      #set      BUSMODE SINGLE_CHIP      ; <<< set bus
                                                    mode (see mode pins)
                                          450
                                          451      #set      MULTIPLEXED     0        ;
                                          452      #set      NON_MULTIPLEXED 1        ; only if sup
                                                   ported by the device
                                          453
                                          454      #set      ADDRESSMODE MULTIPLEXED  ; <<< set add
                                                   ress-mode
                                          455
                                          456      ; Some devices support multiplexed and/or non-mu
_____________________________________________________________________________
F2MC-16 Family SOFTUNE Assembler V30L11       2008-01-06 16:22:06   Page:  14
STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

                                                   ltiplexed Bus mode
                                          457      ; please refer to the related datasheet/hardware
                                                   manual
                                          458
                                          459      #set      ROMMIRROR      ON        ; <<< ROM mir
                                                   ror function ON/OFF
                                          460                                         ;     MB90500
                                                   /400/300/800 family only
                                          461
                                          462      ; In Internal ROM / External Bus mode one can se
                                                   lect whether to mirror
                                          463      ; area FF4000..FFFFFF to 004000..00FFFF. This is
                                                    necessary to get the
                                          464      ; compiler ROMCONST option working. However, if
                                                   ROMCONST is not used,
                                          465      ; this area might be used to access external mem
                                                   ory. This is intended
                                          466      ; to increase performance, if a lot of dynamic d
                                                   ata have to be accessed.
                                          467      ; In SMALL and MEDIUM model these data can be ac
                                                   cessed within bank 0,
                                          468      ; which allows to use near addressing.
                                          469      ; These controller without the ROMM-control regi
                                                   ster always have the
                                          470      ; mirror function on in INROM mode.
                                          471
                                          472      ; If BUSMODE is "SINGLE_CHIP", ignore remaining
                                                   bus settings.
                                          473
                                          474      #set      AUTOWAIT_IO    0         ; <<< 0..3 wa
                                                   itstates for IO area
                                          475      #set      AUTOWAIT_LO    0         ; <<< 0..3 fo
                                                   r lower external area
                                          476      #set      AUTOWAIT_HI    0         ; <<< 0..3 fo
                                                   r higher external area
                                          477
                                          478      #set      ADDR_PINS B'00000000     ; <<< select
                                                   used address lines
                                          479                                         ;     A23..A1
                                                   6 to be output.
                                          480      ; This is the value to be set in HACR-register.
                                                   "1" means: pin used as
                                          481      ; IO-port. (B'10000000 => A23 not used, B'000000
                                                   01 => A16 not used)
                                          482
                                          483      #set      BUS_SIGNAL B'00000100    ; <<< enable
                                                   bus control signals
                                          484      ;                      |||||||+-- ignored
                                          485      ;                      ||||||+--- bus width lowe
                                                   r memory (0:16, 1:8Bit)
                                          486      ;                      |||||+---- output WR sign
                                                   al(s)    (1: enabled  )
                                          487      ;                      ||||+----- bus width uppe
                                                   r memory (0:16, 1:8Bit)
_____________________________________________________________________________
F2MC-16 Family SOFTUNE Assembler V30L11       2008-01-06 16:22:06   Page:  15
STARTUP FILE FOR MEMORY INITIALISATION

SN LOC    OBJ                           LLINE      SOURCE

                                          488      ;                      |||+------ bus width ext
                                                   IO area  (0:16, 1:8Bit)
                                          489      ;                      ||+------- enable HRQ inp
                                                   ut       (1: enabled  )
                                          490      ;                      |+-------- enable RDY inp
                                                   ut       (1: enabled  )
                                          491      ;                      +--------- output CLK sig
                                                   nal      (1:enabled   )
                                          492
                                          493      ; These settings correspond to the EPCR-register
                                                   .
                                          494      ; Hint: Except for MB90500/400/300/800 devices t
                                                   he clock output is
                                          495      ; needed for external RDY synchronisation, if Re
                                                   ady function is used.
                                          496      ; Hint: Don't forget to enable WR signals, if ex
                                                   ternal RAM has to be