📄 xinhao.edf
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(shape (circle BOT 1.27000 0 0))
)
)
(network
(net "#00000"
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(use_layer TOP BOT)
(use_via $VIA_SIGNAL)
)
(pins U1-17 Y1-1 C2-1)
)
(net "#00001"
(circuit
(use_layer TOP BOT)
(use_via $VIA_SIGNAL)
)
(pins U1-18 Y1-0 C1-0)
)
(net "#00005"
(circuit
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(pins U1-8 C3-1 R2-1)
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(net "#00006"
(circuit
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)
(pins U1-38 U2-6)
)
(net "#00007"
(circuit
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(pins U1-37 U2-5)
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(net "#00008"
(circuit
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(pins U1-36 U2-4)
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(net "#00009"
(circuit
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(pins U1-35 U2-3)
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(net "#00010"
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(pins U1-34 U2-15)
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(net "#00011"
(circuit
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(pins U1-33 U2-14)
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(net "#00012"
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(pins U1-32 U2-13)
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(net "#00013"
(circuit
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(pins U1-31 U2-12)
)
(net "#00022"
(circuit
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(pins U1-9 U4-0)
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(net "#00023"
(circuit
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(pins U1-10 U4-1)
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(net "#00024"
(circuit
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(pins U1-11 U4-2)
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(net "#00025"
(circuit
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(pins U1-12 D1-1 D2-1 D3-1 D4-1)
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(net "#00028"
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(use_via $VIA_SIGNAL)
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(pins U1-15 U2-17)
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(circuit
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(circuit
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(pins U1-26 D3-0 R7-0)
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(net "#00046"
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(pins U2-10)
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(net "#00062"
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(pins R3-1)
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(net "+5V"
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(pins U2-7 C3-0 R1-0 R5-1 R6-1 R7-1 R8-1)
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(net "GND"
(circuit
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(pins U1-19 U2-0 U2-1 U2-2 U2-9 U2-11 U2-16 U4-3 U4-4 U4-7 C1-1 C2-0 R2-0)
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(net "VCC/VDD"
(circuit
(use_layer TOP BOT)
(use_via $VIA_POWER)
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(pins U1-39 U2-18 U2-19 U4-5 U4-15)
)
(class POWER
"+5V"
"GND"
"VCC/VDD"
(rule
(width 0.30480)
(clearance 0.38100)
(clearance 0.25400 (type wire_via))
(clearance 0.25400 (type wire_smd))
(clearance 0.25400 (type wire_pin))
(clearance 0.25400 (type wire_wire))
(clearance 0.25400 (type via_pin))
(clearance 0.25400 (type via_via))
(clearance 0.25400 (type via_smd))
)
)
(class SIGNAL
"#00000"
"#00001"
"#00005"
"#00006"
"#00007"
"#00008"
"#00009"
"#00010"
"#00011"
"#00012"
"#00013"
"#00022"
"#00023"
"#00024"
"#00025"
"#00028"
"#00032"
"#00037"
"#00038"
"#00039"
"#00045"
"#00046"
"#00062"
"#00063"
"{NC}"
"{VOID}"
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(clearance 0.25400 (type via_pin))
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(clearance 0.25400 (type via_smd))
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(via PS5 10.16000 52.07000 (net "#00009"))
(via PS5 6.35000 -2.54000 (net "#00032"))
(via PS5 13.97000 49.53000 (net "+5V"))
)
)
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