📄 syslib.c
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/* sysLib.c - Embedded Planet RPX board system-dependent library */
/* Copyright 1984-2001 Wind River Systems, Inc. */
#include "copyright_wrs.h"
/*
modification history
--------------------
01a,12oct01,gev written
*/
/*
DESCRIPTION
This library provides board-specific routines. The chip drivers included are:
ppc860Timer.c - PowerPC/860 Timer library
sysMotCpmEnd.c - configuration module for the motCpmEnd driver
byteNvRam.c - Byte oriented non-volatile RAM driver
INCLUDE FILES: sysLib.h
SEE ALSO:
.pG "Configuration"
*/
/* includes */
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "logLib.h"
#include "stdio.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "private/vmLibP.h"
#include "sys82xxDpramLib.h"
#include "m8260IOPort.h"
#include "smc8260Sio.h"
#include "ep8260.h"
#if !defined(M8260_SIUMCR)
#define M8260_SIUMCR(base) (CAST(VUINT32 *)((base) + 0x10000))
#endif
#if 0
static unsigned long pCoreParams[] = {
0x0A53423D,0x39363030,0x0A424F3D,0x45503832,
0x36300A42,0x523D312E,0x320A5052,0x3D383236,
0x300A5056,0x3D2E0A44,0x313D3634,0x0A44323D,
0x33320A4E,0x563D3132,0x380A5443,0x3D300A53,
0x503D534D,0x43310A49,0x503D3139,0x322E3136,
0x382E3130,0x302E3231,0x0A544950,0x3D31302E,
0x302E302E,0x3138360A,0x45413D30,0x30313045,
0x43303033,0x3231430A,0x58543D36,0x36303030,
0x3030300A,0x53573D30,0x0A0AFFFF,0xFFFFFFFF
};
#endif
/* Global data */
/*
* sysBatDesc[] is used to initialize the block address translation (BAT)
* registers within the PowerPC 603/604 MMU. BAT hits take precedence
* over Page Table Entry (PTE) hits and are faster. Overlap of memory
* coverage by BATs and PTEs is permitted in cases where either the IBATs
* or the DBATs do not provide the necessary mapping (PTEs apply to both
* instruction AND data space, without distinction).
*
* The primary means of memory control for VxWorks is the MMU PTE support
* provided by vmLib and cacheLib. Use of BAT registers will conflict
* with vmLib support. User's may use BAT registers for i/o mapping and
* other purposes but are cautioned that conflicts with caching and mapping
* through vmLib may arise. Be aware that memory spaces mapped through a BAT
* are not mapped by a PTE and any vmLib() or cacheLib() operations on such
* areas will not be effective, nor will they report any error conditions.
*
* Note: BAT registers CANNOT be disabled - they are always active.
* For example, setting them all to zero will yield four identical data
* and instruction memory spaces starting at local address zero, each 128KB
* in size, and each set as write-back and cache-enabled. Hence, the BAT regs
* MUST be configured carefully.
*
* With this in mind, it is recommended that the BAT registers be used
* to map LARGE memory areas external to the processor if possible.
* If not possible, map sections of high RAM and/or PROM space where
* fine grained control of memory access is not needed. This has the
* beneficial effects of reducing PTE table size (8 bytes per 4k page)
* and increasing the speed of access to the largest possible memory space.
* Use the PTE table only for memory which needs fine grained (4KB pages)
* control or which is too small to be mapped by the BAT regs.
*
* The BAT configuration for 4xx/6xx-based PPC boards is as follows:
* All BATs point to PROM/FLASH memory so that end customer may configure
* them as required.
*
* [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
*/
UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
{
/* Contrary to the misguided comments above, ALL the IBATS are being disabled here.... */
0, 0, /* I BAT 0 */
0, 0, /* I BAT 1 */
0, 0, /* I BAT 2 */
0, 0, /* I BAT 3 */
/* use DBAT0 to map the IMMR into data space */
/* NOTE! this space cannot be cached (for data accesses) and should be guarded */
((INTERNAL_MEM_MAP_ADDR & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_128K
| _MMU_UBAT_VS | _MMU_UBAT_VP),
((INTERNAL_MEM_MAP_ADDR & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW
| _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
#define LOCAL_BUS_DBAT_DESC_NUM 0x0a
/* NOTE! the local bus SDRAM cannot be cached -- period -- but does not need guarded */
((LOCAL_BUS_SDRAM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M
| _MMU_UBAT_VS | _MMU_UBAT_VP),
((LOCAL_BUS_SDRAM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW
| _MMU_LBAT_CACHE_INHIBIT),
/* Contrary to the misguided comments above, the unused DBATS are being disabled here.... */
0, 0, /* D BAT 2 */
0, 0, /* D BAT 3 */
};
PHYS_MEM_DESC sysPhysMemDesc [] =
{
/* The following maps the Vector Table and Interrupt Stack */
{
(void *) LOCAL_MEM_LOCAL_ADRS,
(void *) LOCAL_MEM_LOCAL_ADRS,
RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
},
/* The following maps the Local SDRAM */
{
(void *) RAM_LOW_ADRS,
(void *) RAM_LOW_ADRS,
LOCAL_MEM_SIZE - RAM_LOW_ADRS,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
},
{
/* NVRAM window. Note if there is no NVRAM, this may be removed to save a PTE */
(void *) NV_RAM_ADRS,
(void *) NV_RAM_ADRS,
NV_RAM_SIZE,
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) BCSR,
(void *) BCSR,
0x00001000, /* 4 k - Board Control and Status */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{ /* Chuck (PTR Group) Added */
(void *) CS3_ADRS,
(void *) CS3_ADRS,
CS3_SIZE, /* chip select 3 to octart */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{ /* Chuck (PTR Group) Added */
(void *) CS5_ADRS,
(void *) CS5_ADRS,
CS5_SIZE, /* chip select 5 to octart */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{ /* Chuck (PTR Group) Added */
(void *) CS2_ADRS,
(void *) CS2_ADRS,
CS2_SIZE, /* chip select 5 to octart */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
VM_STATE_MASK_GUARDED,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT |
VM_STATE_GUARDED
},
{
(void *) ROM_BASE_ADRS,
(void *) ROM_BASE_ADRS,
ROM_SIZE, /* Flach memory */
VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
}
};
int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);
int sysBus = BUS; /* system bus type (VME_BUS, etc) */
int sysCpu = CPU; /* system CPU type (PPC860) */
char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char *sysExcMsg = EXC_MSG_ADRS; /* catastrophic message area */
int sysProcNum; /* processor number of this CPU */
int sysFlags; /* boot flags */
char sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */
BOOL sysVmeEnable = FALSE; /* by default no VME */
char rpxBootParams[512]; /* we copy PlanetCore boot params here */
LOCAL char sysModelStr[80];
/* Parameters set from the Planet Core boot parameters */
/* NOTE: Changes in the Planet Core boot parameter structure may require changes here */
#define PARAM_MAX_LEN 16
int sysConsoleBaud = 0;
int sysMemSize = LOCAL_MEM_SIZE;
int sysLocalBusMemSize = LOCAL_BUS_SDRAM_SIZE;
int sysNvRamSize = 0;
char sysBoardTypeStr[PARAM_MAX_LEN] = "RPX6"; /* BO */
char sysBoardRevStr[PARAM_MAX_LEN] = "AY"; /* BR */
char sysCpuTypeStr[PARAM_MAX_LEN] = "8260"; /* PR */
char sysCpuVariantStr[PARAM_MAX_LEN]= {NULL};
char sysSerPortStr[PARAM_MAX_LEN] = {NULL};
char sysIP[PARAM_MAX_LEN];
char sysTIP[PARAM_MAX_LEN];
/* forward declarations */
LOCAL void rpxToVxBootParams(char *params);
LOCAL void sysNvRamSetup(void);
LOCAL char *bootParamKeySearch(char *token,char *search_area);
LOCAL void BootlineConfig(void);
/* Chuck (PTR Group) Added: */
int ptrPA28Set(void);
int ptrPA28Clear(void);
int ptrDisableSMCXcvrs(void);
int ptrEnable66MHzClkOut(void);
int ptrDisable66MHzClkOut(void);
int ptrGetBoardID(void);
int ptrBR3Set(unsigned int);
int ptrOR3Set(unsigned int);
int ptrBR5Set(unsigned int);
int ptrOR5Set(unsigned int);
/*
* When using PlanetCore to boot, locally define the nvram routines since the physical size
* of the device is passed via PlanetCore to the BSP rather than being hard coded.
*/
STATUS sysNvRamGet(char *string, int len, int offset);
STATUS sysNvRamSet(char *string, int len, int offset);
/* Forward function references */
UINT32 vxImmrGet (void);
void vxImmrSet (UINT32 value);
void sysClkRateAdjust ( int * );
UINT32 sysChipRev(void);
void sysCpmReset(void);
UINT32 sysCoreFreqGet(void);
UINT32 sysCpmFreqGet(void);
UINT32 sysInputFreqGet(void);
UINT8 sysModckHGet (void);
int sysBoardType (void);
int sysBoardRevision (void);
/*test led*/
void testled(void);
/* import */
IMPORT void sysEnetAddrSet(unsigned char,unsigned char,unsigned char,unsigned char,unsigned char,unsigned char);
/* locals */
LOCAL UINT32 immrAddress = (UINT32) INTERNAL_MEM_MAP_ADDR;
#ifndef HARDCODED_FREQ_PARMS
/* 8260 Reset Configuration Table (From page 9-2 in Rev0 of 8260 book) */
#define END_OF_TABLE 0
LOCAL struct config_parms {
UINT32 inputFreq; /* MODCK_H */
UINT8 modck_h; /* | */
UINT8 modck13; /* |MODCK[1-3] */
UINT32 cpmFreq; /* Input | | CPM Core */
UINT32 coreFreq; /* | | | | | */
} modckH_modck13[] = {/* V V V V V */
{FREQ_33MHZ, 1, 0, FREQ_66MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 1, FREQ_66MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 2, FREQ_66MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 1, 3, FREQ_66MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 1, 4, FREQ_66MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 1, 5, FREQ_100MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 1, 6, FREQ_100MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 1, 7, FREQ_100MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 0, FREQ_100MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 1, FREQ_100MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 2, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 2, 3, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 2, 4, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 2, 5, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 2, 6, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 2, 7, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 0, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 1, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 2, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 3, 3, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_33MHZ, 3, 4, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_33MHZ, 3, 5, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_33MHZ, 3, 6, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_33MHZ, 3, 7, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_33MHZ, 4, 0, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 5, 5, FREQ_133MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 5, 6, FREQ_133MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 5, 7, FREQ_133MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 0, FREQ_133MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 1, FREQ_133MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 6, 2, FREQ_133MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 6, 3, FREQ_166MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 6, 4, FREQ_166MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 6, 5, FREQ_166MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 6, 6, FREQ_166MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 6, 7, FREQ_166MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 0, FREQ_166MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 1, FREQ_200MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 7, 2, FREQ_200MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 7, 3, FREQ_200MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 7, 4, FREQ_200MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 7, 5, FREQ_200MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 7, 6, FREQ_200MHZ, FREQ_300MHZ},
{FREQ_66MHZ, 7, 7, FREQ_233MHZ, FREQ_133MHZ},
{FREQ_66MHZ, 8, 0, FREQ_233MHZ, FREQ_166MHZ},
{FREQ_66MHZ, 8, 1, FREQ_233MHZ, FREQ_200MHZ},
{FREQ_66MHZ, 8, 2, FREQ_233MHZ, FREQ_233MHZ},
{FREQ_66MHZ, 8, 3, FREQ_233MHZ, FREQ_266MHZ},
{FREQ_66MHZ, 8, 4, FREQ_233MHZ, FREQ_300MHZ},
{END_OF_TABLE,0,0,0,0}
};
#endif
#include "sys82xxDpramLib.c"
#include "sysSerial.c"
#include "smc8260Sio.c"
#include "m8260IntrCtl.c"
#include "m8260Timer.c"
#include "sysLed.c"
/* Chuck (PTR Group) Added: */
#include "sc28l198Serial.c"
#include "i2c8260.c"
#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockLib.c"
#endif /* INCLUDE_CACHE_SUPPORT */
#ifdef INCLUDE_NETWORK
#include "sysNet.c"
#endif /* INCLUDE_NETWORK */
/******************************************************************************
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.
*
* RETURNS: A pointer to the string.
*/
char * sysModel (void)
{
sprintf (sysModelStr, "Embedded Planet %s_%s - MPC%s%s",
sysBoardTypeStr, sysBoardRevStr, sysCpuTypeStr, sysCpuVariantStr);
return (sysModelStr);
}
/******************************************************************************
*
* sysBspRev - return the bsp version with the revision eg 1.0/<x>
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