sysmotfccend.c

Embedded Planet公司的ep8260单板计算机的BSP包（VxWorks）

	    intConnect(INUM_TO_IVEC(INUM_IRQ6),sysMiiInt,(int)pPhyInfo);
	    miiIntEnableReg = 0x12;
	    MII_WRITE(pPhyInfo->phyAddr, 18, miiIntEnableReg, tmp);
	    if(tmp == OK){
		intEnable(INUM_IRQ6);
	    }
	}
    }
#endif
    return retVal;
}

/*******************************************************************************
*
* sysFccEnetEnable - enable the MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to enable the Ethernet device and to connect the MII interface to the FCC.
*
* RETURNS: OK, or ERROR if the FCC controller cannot be enabled.
*/
 
STATUS sysFccEnetEnable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
{
  if (fccNum == 3)
  {
    /* set Port B to use MII signals and Port C for clks */

    *BCSR4 &= 0x3f;	/* power down and hold-in-reset the MII PHY */

    *M8260_IOP_PCPAR(immrVal) |=  (PC16 | PC17 | PC27);
    *M8260_IOP_PCSO(immrVal)  &= ~(PC16 | PC17 | PC27);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC16 | PC17);
    *M8260_IOP_PCDIR(immrVal) |=  (PC27);

    *M8260_IOP_PBPAR(immrVal) |= (PB4 | PB5 | PB6 /* | PB7 */ |
                                  PB8 | PB9 | PB10 | PB11 |
				  PB12 | PB13 | PB14 | PB15 | PB16 | PB17);

    *M8260_IOP_PBDIR(immrVal)&= ~(PB8 | PB9 | PB10 | PB11 | PB12 |
                                  PB13 | PB16 | PB17);
    *M8260_IOP_PBDIR(immrVal) |= (PB4 | PB5 | PB6 /* | PB7 */ | PB14 | PB15);
    *M8260_IOP_PBSO(immrVal) &= ~(PB4 | PB5 | PB6 /* | PB7 */ |
                                  PB8 | PB9 | PB10 | PB11 | PB12 |
                                  PB13 | PB14 | PB15 | PB16 | PB17);

    /* connect FCC3 clocks */

    *M8260_CMXFCR (immrVal)  |= (0x00003700);
    *M8260_CMXFCR (immrVal)  &= ~(0x00004000);

    *BCSR4 |= 0xC0;	/* power up and UN reset the MII PHY */

  }
  else /* fccNum == 2 */
  {
    /* Power down the phy via PA28.
     * Reset the phy via PA27.
     */
    *M8260_IOP_PADAT( immrVal ) |=  (PA28);
    *M8260_IOP_PADAT( immrVal ) &= ~(PA27);

    /* CLK13 and CLK14 */
    *M8260_IOP_PCPAR(immrVal) |=  (PC18 | PC19);
    *M8260_IOP_PCSO(immrVal)  &= ~(PC18 | PC19);
    *M8260_IOP_PCDIR(immrVal) &= ~(PC18 | PC19);

    /* Set up port B for MII signals. */
    *M8260_IOP_PBPAR(immrVal) |=  (PB18 | PB19 | PB20 | PB21 | PB22 | PB23 |
                                   PB24 | PB25 | PB26 | PB27 | PB28 | PB29 |
                                   PB30 | PB31);
    *M8260_IOP_PBSO(immrVal) &=  ~(PB18 | PB19 | PB20 | PB21 | PB22 | PB23 |
                                   PB24 | PB25 | PB26 | PB27 | PB28 |
                                   PB30 | PB31);
    *M8260_IOP_PBSO(immrVal)  |=  (PB29);
    *M8260_IOP_PBDIR(immrVal) &= ~(PB18 | PB19 | PB20 | PB21 |
                                   PB26 | PB27 | PB28 | PB30);
    *M8260_IOP_PBDIR(immrVal) |=  (PB22 | PB23 | PB24 | PB25 | PB29 | PB31);

    /* connect FCC2 clocks */

    *M8260_CMXFCR (immrVal)  |=  (0x00250000);
    *M8260_CMXFCR (immrVal)  &= ~(0x00400000);

    /* Power up the phy via PA28.
     * Un-reset the phy via PA27.
     */
    *M8260_IOP_PADAT( immrVal ) &= ~(PA28);
    *M8260_IOP_PADAT( immrVal ) |=  (PA27);

  }

  taskDelay(sysClkRateGet());
  _func_motFccPhyInit = (FUNCPTR) sysMiiPhyInit;
  _func_motFccPhyDuplex = (FUNCPTR) sysMiiPhyDuplex;

  return OK;
}
 
/*******************************************************************************
*
* sysFccEnetDisable - disable MII interface to the FCC controller
*
* This routine is expected to perform any target specific functions required
* to disable the Ethernet device and the MII interface to the FCC
* controller.  This involves restoring the default values for all the Port
* B and C signals.
*
* RETURNS: OK, always.
*/
 
STATUS sysFccEnetDisable
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum		/* FCC being used */
    )
{
  int intLevel = intLock();
 
  if (fccNum == 3)
  {
    /* 
     * de-configure all Port B and C pins previously used for FCC3.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC16 | PC17 | PC27);
    *M8260_IOP_PBPAR(immrVal) &= ~(PB4 | PB5 | PB6 /* | PB7 */ | PB8 |
                                   PB9 | PB10 | PB11 | PB12 | PB13 | PB14 |
                                   PB15 | PB16 | PB17);

#if 0
    /* Disable the interrupt */
    intDisable (INUM_FCC3);
#endif

    *BCSR4 &= 0x3f;	/* power down and hold-in-reset the MII PHY */

  }
  else  /* fccNum == 2 */
  {
    /* 
     * de-configure all Port B and C pins previously used for FCC2.
     */

    *M8260_IOP_PCPAR(immrVal) &= ~(PC18 | PC19);
    *M8260_IOP_PBPAR(immrVal) &= ~(PB18 | PB19 | PB20 | PB21 | PB22 | PB23 |
                                   PB24 | PB25 | PB26 | PB27 | PB28 | PB29 |
                                   PB30 | PB31);

#if 0
    /* Disable the interrupt */
    intDisable (INUM_FCC2);
#endif

    /* Power down the phy via PA28.
     * Reset the phy via PA27.
     */
    *M8260_IOP_PADAT( immrVal ) |=  (PA28);
    *M8260_IOP_PADAT( immrVal ) &= ~(PA27);

  }

  intUnlock (intLevel);
  return OK;
}
 
/*******************************************************************************
*
* sysFccEnetAddrGet - get the hardware Ethernet address
*
* This routine provides the six byte Ethernet hardware address that will be
* used by each individual FCC device unit.  This routine must copy
* the six byte address to the space provided by <addr>.
*
* RETURNS: OK, or ERROR if the Ethernet address cannot be returned.
*/

STATUS sysFccEnetAddrGet
    (
    int  unit ,       /* not used - only slave SCC1 is wired to port */
    UINT8 *  addr     /* Location address is returned in */
    )
{
STATUS status;

    /* Get MAC address */
    status = sysEnetAddrGet(unit, addr);
    return status;
}

/*******************************************************************************
*
* sysFccEnetCommand - issue a command to the Ethernet interface controller
*
* RETURNS: OK, or ERROR if the Ethernet controller could not be restarted.
*/

STATUS sysFccEnetCommand
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    UINT16	command
    )
    {
    return (OK);
    }

#ifndef MOTOROLA_FCC_LOOP_NS
  #define MOTOROLA_FCC_LOOP_NS 4
#endif

void NSDELAY(nsec)
{
volatile int nx = 0;
volatile int loop = (int)(nsec*MOTOROLA_FCC_LOOP_NS);
    for (nx = 0; nx < loop; nx++);
}

/**************************************************************************
*
* sysFccMiiBitWr - write one bit to the MII interface
*
* This routine writes the value in <bitVal> to the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
* If <bitVal> is NONE, then the MDIO pin should be left in high-impedance
* state.
*
* SEE ALSO: sysFccMiiBitRd()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitWr
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT32        bitVal          /* the bit being written */
    )
{
  miiBitWrCount++; 

  /* 
   * We create , in software, the timing for MDIO data transfers.
   */

  if (fccNum == 3)
  {
    /* 
     * MDIO and MDC are part of BCSR4.
     */

    *BCSR4 &= ~(BCSR4_MII_WR|BCSR4_MII_MDC|BCSR4_MII_MDIO);
    switch(bitVal){
	case 0:
	    *BCSR4 &= ~BCSR4_MII_MDIO;
	    break;
	case 1:
	    *BCSR4 |= BCSR4_MII_MDIO;
	    break;
	case ((INT32) NONE):
	    /* put it in high-impedance state */
	    *BCSR4 |= (BCSR4_MII_WR|BCSR4_MII_MDC);
	    *BCSR4 &= ~BCSR4_MII_MDIO;
	    return OK;
	default:
	    return ERROR;
    }
    *BCSR4 |= BCSR4_MII_MDC;
    NSDELAY (200);
    /* now we toggle the clock and delay again */
    *BCSR4 &= ~BCSR4_MII_MDC;
    NSDELAY (200);
  }
  else /* fccNum == 2 */
  {
    /*
     * MDIO and MDC are on port C.
     */

    /* set MDIO to be an output */
    *M8260_IOP_PCDIR( immrVal ) |= (PC9);

    /* MDC = 0
     * MDIO = 0
     */
    *M8260_IOP_PCDAT( immrVal ) &= ~(PC9 | PC10);

    switch(bitVal){
	case 0:
            /* MDIO=0 */
            *M8260_IOP_PCDAT( immrVal ) &= ~(PC9);
	    break;
	case 1:
            /* MDIO=1 */
            *M8260_IOP_PCDAT( immrVal ) |= (PC9);
	    break;
	case ((INT32) NONE):
	    /* put it in high-impedance state */

            /* set MDIO to be an input */
            *M8260_IOP_PCDIR( immrVal ) &= ~(PC9);

            /* MDC=1
             * MDIO=0
             */
            *M8260_IOP_PCDAT( immrVal ) |= (PC10);
            *M8260_IOP_PCDAT( immrVal ) &= ~(PC9);

	    return OK;
	default:
	    return ERROR;
    }

    /* MDC=1
     */
    *M8260_IOP_PCDAT( immrVal ) |= (PC10);
    NSDELAY (200);

    /* now we toggle the clock and delay again */

    /* MDC=0
     */
    *M8260_IOP_PCDAT( immrVal ) &= ~(PC10);
    NSDELAY (200);
  }

  return OK;
}
 
/**************************************************************************
*
* sysFccMiiBitRd - read one bit from the MII interface
*
* This routine reads one bit from the MDIO line of a MII
* interface. The MDC line is asserted for a while, and then negated.
*
* SEE ALSO: sysFccMiiBitWr()
*
* RETURNS: OK, or ERROR.
*/

STATUS sysFccMiiBitRd
    (
    UINT32      immrVal,      	/* base address of the on-chip RAM */
    UINT8	fccNum,		/* FCC being used */
    INT8 *      bitVal          /* the bit being read */
    )
{
  miiBitRdCount++; 

  /* 
   * We create , in software, the timing for MDIO data transfers.
   */

  if (fccNum == 3)
  {
    /*
     * MDIO and MDC are part of BCSR4.
     */

    *BCSR4 |= (BCSR4_MII_WR|BCSR4_MII_MDC);
    NSDELAY (200);

    /* we can now read the MDIO data from BCSR4 */
    *bitVal = *BCSR4;

    /* now we toggle the clock and delay again */
    *BCSR4 &= ~BCSR4_MII_MDC;

    NSDELAY (200);
  }
  else /* fccNum == 2 */
  {
    /*
     * MDIO and MDC are on port C.
     */

    /* set MDIO to be an input */
    *M8260_IOP_PCDIR( immrVal ) &= ~(PC9);

    /* MDC=1
     */
    *M8260_IOP_PCDAT( immrVal ) |= (PC10);
    NSDELAY (200);

    /* we can now read the MDIO data from BCSR4 */
    {
      unsigned int wordVal;
      wordVal = *M8260_IOP_PCDAT( immrVal );  /* Read port C                */
      wordVal &= PC9;                         /* Get MDIO bit               */
      wordVal >>= 22;                         /* Shift it to be the LSB     */
      *bitVal = (wordVal & 1);                /* Return the bit of interest */
    }

    /* now we toggle the clock and delay again */

    /* MDC=0
     */
    *M8260_IOP_PCDAT( immrVal ) &= ~(PC10);

    NSDELAY (200);
  }

  return OK;
}

#endif /* INCLUDE_MOT_FCC */