rominit.s

Embedded Planet公司的ep8260单板计算机的BSP包（VxWorks）

/* romInit.s - PPC 8XX ROM initialization module for PlanetCore on RPX Boards */

/* Copyright 1984-1998 Wind River Systems, Inc. */
/* Copyright 1996-1998 Motorola, Inc. */
/* Copyright 2001 Embedded Planet, Inc. */


/*
DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

For Embedded Planet RPX boards, this code is reached after the board is
initially booted with PlanetCore.  Thus, very little initialization is required --
all hardware-specific init (such as DRAM timing, clock setup, etc.) is
performed by PlanetCore.  Other hardware and device initialization is
performed later in the BSP's sysHwInit() routine.

A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().

WARNING:
This code must be Position Independent Code (PIC).  This means that it
should not contain any absolute address references.  If an absolute address
must be used, it must be relocated by the macro ROM_ADRS(x).  This macro
will convert the absolute reference to the appropriate address within
ROM space no matter how the boot code was linked. (For PPC, ROM_ADRS does
not work.  You must subtract _romInit and add ROM_TEXT_ADRS to each
absolute address).

This code should not call out to subroutines declared in other modules,
specifically sysLib.o, and sysALib.o.  If an outside module is absolutely
necessary, it can be linked into the system by adding the module 
to the makefile variable BOOT_EXTRA.  If the same module is referenced by
other BSP code, then that module must be added to MACH_EXTRA as well.
Note that some C compilers can generate code with absolute addresses.
Such code should not be called from this module.  If absolute addresses
cannot be avoided, then only ROM resident code can be generated from this
module.  Compressed and uncompressed bootroms or VxWorks images will not
work if absolute addresses are not processed by the macro ROM_ADRS.

*/

/* defines */

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "ep8260.h"
#include "regs.h"
#include "sysLib.h"
#include "config.h"
#include "drv/timer/m8260Clock.h"
#include "drv/mem/m8260Siu.h"
#include "drv/mem/m8260Memc.h"	

/* Can't use ROM_ADRS macro with HIADJ and LO macro functions, for PPC */

	/* Exported internal functions */

	.data
	.globl	_romInit	/* start of system code */
	.globl	romInit		/* start of system code */
	.globl	_romInitWarm	/* start of system code */
	.globl	romInitWarm	/* start of system code */

	/* externals */

	.extern romStart	/* system initialization routine */

	.text
	.align 2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType	/@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:

	/*
	 * After exiting the Planet Core boot loader, r3 contains the location in DPRAM where
	 * the boot loader has saved the boot parameters for use in building the vxWorks boot
	 * line.  We store this at 0x00003000 very briefly until it can be picked up by
	 * sysHwInit().
	 */

	lis     	r6, HIADJ(0x00003000)
	addi    	r6, r6, LO(0x00003000)
	stw		r3, 0(r6)

	bl	cold		/* jump to the cold boot initialization */
/*	nop */
	
_romInitWarm:
romInitWarm:
	
	/*
	 * If this is a warm boot, skip over some initialization.
	 */

	bl	start		/* jump to the warm boot initialization */

	/* copyright notice appears at beginning of ROM (in TEXT segment) */

	.ascii   "Copyright 1984-1998 Wind River Systems, Inc."
	.align 2

cold:
	li	r3, BOOT_COLD	/* set cold boot as start type */

	/*
	 * disable external interrupts and Instruction/Data MMU, set
	 * the exception prefix 
	 */
start:
    /* disable external interrupts (by zeroing out msr) */
	xor	    r5,r5,r5
	isync  
	mtmsr	r5
	isync  

	/* invalidate and disable the MPU's data/instruction caches */
	mfspr	r6,HID0
	ori	    r5,r5,0xC000
	andc	r6,r6,r5	 /* clear cache enable bits in r6 */
	mr	    r5,r6
	ori	    r5,r5,0xCC00 /* r5 has DCE,ICE,ICFI,DCFI set */
	sync
	mtspr	HID0,r5		/* invalidate both caches with 2 stores */
	mtspr	HID0,r6		/* leaving them both disabled */
	isync

	mtspr   SPRG0,r3
	bl	    romClearBATs
	bl	    romInvalidateTLBs
	bl	    romClearSegs
	bl	    romClearFPRegs
	mfspr   r3,SPRG0

        /* Zero-out registers: r0 & SPRGs */
	xor	    r0,r0,r0
	mtspr	SPRG0,r0
	mtspr	SPRG1,r0
	mtspr	SPRG2,r0
	mtspr	SPRG3,r0

	/* MSR: clear EE,DR,IR -- set ME,RI	*/
	ori	    r4,r0,0x1002
	mtmsr   r4
	isync 

#if 0
	/* disable all devices (serial, ethernet, ...) */
	lis		r4, HIADJ(BCSR_RESET_VAL)
	lis		r5, HIADJ (BCSR)
	stw		r4, LO(BCSR)(r5)		/* reset the BCSR register */
#endif

        /* initialize r2 and r13 according to EABI standard */

	/* go to C entry point */

	LOADPTR (sp, STACK_ADRS)

	/* initialize the stack pointer */
	addi	sp, sp, -FRAMEBASESZ		/* get frame stack */

	/* 
	 * calculate C entry point: routine - entry point + ROM base 
	 * routine	= romStart
	 * entry point	= romInit	= R7
	 * ROM base	= ROM_TEXT_ADRS = R8
	 * C entry point: romStart - R7 + R8 
	 */

	LOADPTR (r7, romInit)
	LOADPTR (r8, ROM_TEXT_ADRS)
	LOADPTR (r6, romStart)
	sub	r6, r6, r7			/* routine - entry point */
	add	r6, r6, r8 			/* + ROM base */

	mtlr	r6				/* move C entry point to LR */
	blr					/* jump to the C entry point */

/*******************************************************************************
*
* romClearBATs - 
*
* This routine will zero the BAT registers.
*
* RETURNS: None
*
*/

romClearBATs:			/* zero out the BAT registers */
	xor		r5,r5,r5
	isync
	mtspr	IBAT0U,r5	/* clear all upper BATS first */
	mtspr	IBAT1U,r5
	mtspr	IBAT2U,r5
	mtspr	IBAT3U,r5
	mtspr	DBAT0U,r5
	mtspr	DBAT1U,r5
	mtspr	DBAT2U,r5
	mtspr	DBAT3U,r5

	mtspr	IBAT0L,r5	/* then clear lower BATS */
	mtspr	IBAT1L,r5
	mtspr	IBAT2L,r5
	mtspr	IBAT3L,r5
	mtspr	DBAT0L,r5
	mtspr	DBAT1L,r5
	mtspr	DBAT2L,r5
	mtspr	DBAT3L,r5
	isync

	blr

/*******************************************************************************
*
* romClearSegs - 
*
* This routine will zero the MMU's segment registers.
*
* RETURNS: None
*
*/

romClearSegs:		/* Init the Segment registers */
	xor	    r5, r5, r5
	isync
	mtsr	0,r5
	mtsr	1,r5
	mtsr	2,r5
	mtsr	3,r5
	mtsr	4,r5
	mtsr	5,r5
	mtsr	6,r5
	mtsr	7,r5
	mtsr	8,r5
	mtsr	9,r5
	mtsr	10,r5
	mtsr	11,r5
	mtsr	12,r5
	mtsr	13,r5
	mtsr	14,r5
	mtsr	15,r5
	isync

	blr

/*******************************************************************************
*
* romInvalidateTLBs - 
*
* This routine will invalidate the BAT's register.
*
* RETURNS: None
*
*/

romInvalidateTLBs:
	isync
	/* invalidate entries within both TLBs */
	li	    r5,128
	mtctr	r5		 /* CTR = 32  */
	xor	    r5,r5,r5
	isync			 /* context sync req'd before tlbie */

tlbloop:
	tlbie	r5
	sync			     /* sync instr req'd after tlbie      */
	addi	r5,r5,0x1000 /* increment bits 15-19              */
	bdnz	tlbloop		 /* decrement CTR, branch if CTR != 0 */
	isync
	blr


/*******************************************************************************
*
* romClearFPRegs
*
* This routine will initialize the FPU's registers.
*
* RETURNS: None
*
*/

romClearFPRegs:
	mflr	r30
	
	/* Turn on FP */
    li	    r3,0x2000
    mtmsr   r3
    sync

    /* Init the floating point control/status register */
    mtfsfi  7,0x0
    mtfsfi  6,0x0
    mtfsfi  5,0x0
    mtfsfi  4,0x0
    mtfsfi  3,0x0
    mtfsfi  2,0x0
    mtfsfi  1,0x0
    mtfsfi  0,0x0
    isync

    /* Initialize the floating point data registers to a known state */

    bl      ifpdrValue
    .long   0x3f800000      /* 1.0 */

ifpdrValue:
    mflr    r3
    lfs     f0,0(r3)
    lfs     f1,0(r3)
    lfs     f2,0(r3)
    lfs     f3,0(r3)
    lfs     f4,0(r3)
    lfs     f5,0(r3)
    lfs     f6,0(r3)
    lfs     f7,0(r3)
    lfs     f8,0(r3)
    lfs     f9,0(r3)
    lfs     f10,0(r3)
    lfs     f11,0(r3)
    lfs     f12,0(r3)
    lfs     f13,0(r3)
    lfs     f14,0(r3)
    lfs     f15,0(r3)
    lfs     f16,0(r3)
    lfs     f17,0(r3)
    lfs     f18,0(r3)
    lfs     f19,0(r3)
    lfs     f20,0(r3)
    lfs     f21,0(r3)
    lfs     f22,0(r3)
    lfs     f23,0(r3)
    lfs     f24,0(r3)
    lfs     f25,0(r3)
    lfs     f26,0(r3)
    lfs     f27,0(r3)
    lfs     f28,0(r3)
    lfs     f29,0(r3)
    lfs     f30,0(r3)
    lfs     f31,0(r3)
    sync
	
	mtlr	r30
	bclr	20,0		/* Return to caller */