📄 syscachelocklib.c
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/* sysCacheLockLib.c - Cache locking support routines. *//* Copyright 2000 Wind River, Inc *//*modification history--------------------
01a,12Dec00,mno created (teamf1)*//*DESCRIPTIONThis module contains code to lock and unlock L1 cache. The routinessysCacheLock/Unlock can be used to lock and unlock the L1 cache.This module supports PPC processors that support separate data and instructioncaches (harward-style) for the L1. The lock routine will lock the entirecache, after loading it with specified code or data region. When the cache islocked, data/instruction access to regions not locked in the cache will nothit the cache.L1 locking routines can be used to lock only one region of memory. Multiplecalls to lock a region will result in unlocking the previous regionn. Theregion being locked must be aligned on a 32-byte boundary, and must not belarger than the L1 cache size.The region being locked in the L1 cache must be alignedon a 32-byte boundary.SEE ALSO: *//* includes */#include "vxWorks.h"#include "cacheLib.h"#include "intLib.h"#include "string.h"#include "vmLib.h"#include "private/vmLibP.h"#include "arch/ppc/mmuPpcLib.h"#include "tickLib.h"#include "sysCacheLockLib.h"/* externs */IMPORT STATUS cachePpcDisable(CACHE_TYPE cache);/* defines */
#ifndef __DCC__
#define CACHE_LOCK_AND_ENABLE_RTN_SIZE (SYSL1CACHELOCK_ENDADRS - \
SYSL1CACHELOCK_STARTADRS)
#else
#define CACHE_LOCK_AND_ENABLE_RTN_SIZE ((char*)SYSL1CACHELOCK_ENDADRS - \
(char*)SYSL1CACHELOCK_STARTADRS)
#endif /* __DCC__ */
/************************************************************************* sysCacheLock - locks specified data/instruction region** This routine locks the specified region into the cache, <cacheType>. The* region to be locked is specified by the start address, <adrs>, and the size,* <bytes>. The region -- the start address, and size -- must be aligned on a* 32-byte boundary.** Multiple calls to this routine will silently unlock the specified cache to* lock the new region.** RETURN - OK or error if cache is locked, or if cache is not supported.*/STATUS sysCacheLock ( CACHE_TYPE cacheType, void * adrs, UINT32 bytes ) { int x; VOIDFUNCPTR cacheEnableAndLockRtn; UINT32 cacheEnableAndLockRtnSize; if (!ALIGNED(adrs, 32)) { logMsg("\n Memory Address not aligned on 32 byte boundry\n",1,2,3,4,5,6); return (ERROR); } if ((cacheType != _INSTRUCTION_CACHE) && (cacheType != _DATA_CACHE)) return (ERROR); x=intLock(); /* if l1 is locked, unlock it */ if ((vxHid0Get() & _PPC_HID0_DLOCK) || (vxHid0Get() & _PPC_HID0_ILOCK)) sysCacheUnlock(cacheType); cachePpcDisable(cacheType); if (cacheType == _DATA_CACHE) cacheEnableAndLockRtn = _sysL1CacheLock; else { cacheEnableAndLockRtnSize = ROUND_UP(CACHE_LOCK_AND_ENABLE_RTN_SIZE, MMU_PPC_PAGE_SIZE); cacheEnableAndLockRtn = (VOIDFUNCPTR) cacheDmaMalloc (cacheEnableAndLockRtnSize); if (cacheEnableAndLockRtn == NULL) { intUnlock (x); return (ERROR); } VM_STATE_SET (NULL, (char *) cacheEnableAndLockRtn, cacheEnableAndLockRtnSize, VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY, VM_STATE_CACHEABLE_NOT | VM_STATE_MEM_COHERENCY_NOT); bcopy ((char*)SYSL1CACHELOCK_STARTADRS, (char *)cacheEnableAndLockRtn, CACHE_LOCK_AND_ENABLE_RTN_SIZE); } cacheEnableAndLockRtn (cacheType, adrs, bytes); intUnlock(x); if (cacheType == _INSTRUCTION_CACHE) cacheDmaFree ((char *)cacheEnableAndLockRtn); return (OK); }/****************************************************************************** sysCacheUnlock - Unlocks the previous locked cache** This routines unlocks the specified cache, <cacheType>** RETURN - OK or error if cache is not supported.*/STATUS sysCacheUnlock ( CACHE_TYPE cacheType ) { int x; if ((cacheType != _INSTRUCTION_CACHE) && (cacheType != _DATA_CACHE)) return (ERROR); x = intLock(); _sysL1CacheUnlock (cacheType); intUnlock(x); return (OK); }
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