rpx.h

Embedded Planet公司的ep8260单板计算机的BSP包（VxWorks）

/* rpx.h - Embedded Planet RPX board header */

/* Copyright 1984-1997 Wind River Systems, Inc. */

/*
modification history
--------------------
000,15May01,gad  Added CLLF_BW31 board support
01m,22Jun00,cmh  modified ADS860 BSP for RPX boards
01l,06feb99,cn   added support for SDRAM (SPR# 24337), also changed
		 number of SIO channels to 2 (SPR# 10005).
01i,06jan99,cn   added support for FADS860T boards.
01h,18feb98,gls  added support for PPC823FADS
01g,12nov97,map  added SYS_CPU_FREQ [SPR# 9366]
01f,11nov97,hdn  added PC_xxx macros for TFFS.
01e,10nov96,tpr  replaved SYS_CLK_FREQ by SPLL_FREQ_REQUESTED.
01d,08nov96,tpr  added DEC_CLOCK_FREQ.
01c,06nov96,tpr  added macros + clean up.
01b,28may96,dzb  changed to 24Mhz clock speed.
01a,19apr96,tpr  written.
*/

/*
This file contains I/O addresses and related constants for the
RPX Boards.
*/

#ifndef	INCrpxh
#define	INCrpxh

#include "drv/mem/memDev.h"

#ifndef _ASMLANGUAGE
#include "ctype.h"
#endif

#define BUS	0		/* bus-less board */

/*
 * Refresh value - defines the number of BRGCLK period between two
 * DRAM refresh cycle.
 */

#define REFRESH_VALUE	(BRGCLK_FREQ / DRAM_REFRESH_FREQ)

/*
 * Periodic Timer A period - value used to set the PTA bits of
 * the Machine A Mode Register (MAMR). This register is used to
 * controle the User_Programmable Machine A (UPM). The UPM is part of
 * the memory controller.
 */

#define PTA_VALUE	(( REFRESH_VALUE / 64) != 0 ? (REFRESH_VALUE / 64) : \
			 ((REFRESH_VALUE / 32) != 0 ? (REFRESH_VALUE / 32) : \
			 ((REFRESH_VALUE / 16) != 0 ? (REFRESH_VALUE / 16) : \
			 ((REFRESH_VALUE /  8) != 0 ? (REFRESH_VALUE /  8) : \
			 ((REFRESH_VALUE /  4) != 0 ? (REFRESH_VALUE /  4) : \
			  (REFRESH_VALUE /  2))))))

/*
 * Periodic Timer Prescaler Division Factor - gives the division factor
 * of the Periodic Timer Prescaler (PTP). The PTP is part of the
 * memory controller. It divide the BRGCLK (Baud Rate Generator Clock) by
 * either 2, 4, 8, 16, 32 or 64 and send this divided clock to the
 * Periodic Timer.
 * This macro is used to set the DRAM refresh cycle period.
 */

#define PTP_DIV_FACTOR	(REFRESH_VALUE / PTA_VALUE)

/*
 * PTP Value - translate the Periodic Timer Prescaler Division Factor
 * to the value to place in the PTP register.
 */

#define PTP_VALUE	( PTP_DIV_FACTOR ==  2 ? MPTPR_PTP_DIV2 : \
			 (PTP_DIV_FACTOR ==  4 ? MPTPR_PTP_DIV4 : \
			 (PTP_DIV_FACTOR ==  8 ? MPTPR_PTP_DIV8 : \
			 (PTP_DIV_FACTOR == 16 ? MPTPR_PTP_DIV16 : \
			 (PTP_DIV_FACTOR == 32 ? MPTPR_PTP_DIV32 : \
			  MPTPR_PTP_DIV64)))))

/* */

/* define the decrementer input clock frequency */
#define DEC_CLOCK_FREQ	66666666

#define PARTNUM_MASK  0x0000FF00			    /* part number file in IMMR */

/* Board Status and Control Registers - unique to rpx */

#define	BCSR_BASE_ADDR	0xFA000000	/* BCSR base address */

#ifdef _ASMLANGUAGE
#define BCSR	BCSR_BASE_ADDR 		/* BCSR address */
#define BCSR0	BCSR_BASE_ADDR 		/* BCSR address */
#define BCSR1	BCSR_BASE_ADDR + 0x01	/* Register 1 */
#define BCSR2	BCSR_BASE_ADDR + 0x02	/* Register 2 */
#define BCSR3	BCSR_BASE_ADDR + 0x03	/* Register 3 */
#define BCSR4	BCSR_BASE_ADDR + 0x04	/* Register 4 */
#else
#define BCSR	((VINT8 *) (BCSR_BASE_ADDR))		/* BCSR address */
#define BCSR0	((VINT8 *) (BCSR_BASE_ADDR))		/* Register 0 */
#define BCSR1	((VINT8 *) (BCSR_BASE_ADDR + 0x01))	/* Register 1 */
#define BCSR2	((VINT8 *) (BCSR_BASE_ADDR + 0x02))	/* Register 2 */
#define BCSR3	((VINT8 *) (BCSR_BASE_ADDR + 0x03))	/* Register 3 */
#define BCSR4	((VINT8 *) (BCSR_BASE_ADDR + 0x04))	/* Register 4 */
#endif	/* _ASMLANGUAGE */

/* RPX6 (BW) - Board control and status register bit definitions */

/* BCSR0 */
#define BCSR1_SMC_SEL0	0x80
#define BCSR1_SMC_SEL1	0x40
#define BCSR1_SMC_RTS	0x20
#define BCSR1_SMC_CTS	0x10
#define BCSR1_SSON	0x08
#define BCSR1_MW	0x04
#define BCSR1_RSTCONF	0x02

/* BCSR1 */

/* BCSR2 */

/* BCSR3 */

/* BCSR4 */
#define BCSR4_ETHEN	0x80
#define BCSR4_MII_PWR	0x40
#define BCSR4_MII_WR	0x04
#define BCSR4_MII_MDC	0x02
#define BCSR4_MII_MDIO	0x01

/*
 * Board Control and Status Register reset value. Used in sysALib.s to place the board in a
 * stable state for vxWorks bring up.
 *
 * NOTE: This value MUST be set by the user to match the type of board in use for proper
 *       operation
 */

#define BCSR_RESET_VAL

#endif /* INCrpxh */