dual_xlatch16.vhd

fast fourior transform

-- ACTIVE-CAD-2-VHDL, 2.5.5.50, Fri Dec 11 22:19:41 1998

--*****由4个reg16构成一个双端口锁存器。*****

library IEEE;
use IEEE.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity DUAL_XLATCH16 is port (
	D0I : in STD_LOGIC_VECTOR (15 downto 0);
	D0R : in STD_LOGIC_VECTOR (15 downto 0);
	D1I : in STD_LOGIC_VECTOR (15 downto 0);
	D1R : in STD_LOGIC_VECTOR (15 downto 0);
	Q0I : out STD_LOGIC_VECTOR (15 downto 0);
	Q0R : out STD_LOGIC_VECTOR (15 downto 0);
	Q1I : out STD_LOGIC_VECTOR (15 downto 0);
	Q1R : out STD_LOGIC_VECTOR (15 downto 0);
	CE0 : in STD_LOGIC;
	CE1 : in STD_LOGIC;
	CLK : in STD_LOGIC;
	CE : in STD_LOGIC;
	R : in STD_LOGIC
); end DUAL_XLATCH16;

architecture SCHEMATIC of DUAL_XLATCH16 is

--COMPONENTS

component AND2 port (
	I0 : in STD_LOGIC;
	I1 : in STD_LOGIC;
	O : out STD_LOGIC
); end component;

component REG16 port (
	D : in STD_LOGIC_VECTOR (15 downto 0);
	Q : out STD_LOGIC_VECTOR (15 downto 0);
	C : in STD_LOGIC;
	CE : in STD_LOGIC;
	CLR : in STD_LOGIC
); end component;

--SIGNALS

signal CEN1 : STD_LOGIC;
signal CEN0 : STD_LOGIC;


begin

--SIGNAL ASSIGNMENTS


--COMPONENT INSTANCES

G2 : AND2 port map(
	I0 => CE1,
	I1 => CE,
	O => CEN1
);
G1 : AND2 port map(
	I0 => CE0,
	I1 => CE,
	O => CEN0
);
L0 : REG16 port map(
	D(15) => D0R(15),
	D(14) => D0R(14),
	D(13) => D0R(13),
	D(12) => D0R(12),
	D(11) => D0R(11),
	D(10) => D0R(10),
	D(9) => D0R(9),
	D(8) => D0R(8),
	D(7) => D0R(7),
	D(6) => D0R(6),
	D(5) => D0R(5),
	D(4) => D0R(4),
	D(3) => D0R(3),
	D(2) => D0R(2),
	D(1) => D0R(1),
	D(0) => D0R(0),
	Q(15) => Q0R(15),
	Q(14) => Q0R(14),
	Q(13) => Q0R(13),
	Q(12) => Q0R(12),
	Q(11) => Q0R(11),
	Q(10) => Q0R(10),
	Q(9) => Q0R(9),
	Q(8) => Q0R(8),
	Q(7) => Q0R(7),
	Q(6) => Q0R(6),
	Q(5) => Q0R(5),
	Q(4) => Q0R(4),
	Q(3) => Q0R(3),
	Q(2) => Q0R(2),
	Q(1) => Q0R(1),
	Q(0) => Q0R(0),
	C => CLK,
	CE => CEN0,
	CLR => R
);
L1 : REG16 port map(
	D(15) => D0I(15),
	D(14) => D0I(14),
	D(13) => D0I(13),
	D(12) => D0I(12),
	D(11) => D0I(11),
	D(10) => D0I(10),
	D(9) => D0I(9),
	D(8) => D0I(8),
	D(7) => D0I(7),
	D(6) => D0I(6),
	D(5) => D0I(5),
	D(4) => D0I(4),
	D(3) => D0I(3),
	D(2) => D0I(2),
	D(1) => D0I(1),
	D(0) => D0I(0),
	Q(15) => Q0I(15),
	Q(14) => Q0I(14),
	Q(13) => Q0I(13),
	Q(12) => Q0I(12),
	Q(11) => Q0I(11),
	Q(10) => Q0I(10),
	Q(9) => Q0I(9),
	Q(8) => Q0I(8),
	Q(7) => Q0I(7),
	Q(6) => Q0I(6),
	Q(5) => Q0I(5),
	Q(4) => Q0I(4),
	Q(3) => Q0I(3),
	Q(2) => Q0I(2),
	Q(1) => Q0I(1),
	Q(0) => Q0I(0),
	C => CLK,
	CE => CEN0,
	CLR => R
);
L2 : REG16 port map(
	D(15) => D1R(15),
	D(14) => D1R(14),
	D(13) => D1R(13),
	D(12) => D1R(12),
	D(11) => D1R(11),
	D(10) => D1R(10),
	D(9) => D1R(9),
	D(8) => D1R(8),
	D(7) => D1R(7),
	D(6) => D1R(6),
	D(5) => D1R(5),
	D(4) => D1R(4),
	D(3) => D1R(3),
	D(2) => D1R(2),
	D(1) => D1R(1),
	D(0) => D1R(0),
	Q(15) => Q1R(15),
	Q(14) => Q1R(14),
	Q(13) => Q1R(13),
	Q(12) => Q1R(12),
	Q(11) => Q1R(11),
	Q(10) => Q1R(10),
	Q(9) => Q1R(9),
	Q(8) => Q1R(8),
	Q(7) => Q1R(7),
	Q(6) => Q1R(6),
	Q(5) => Q1R(5),
	Q(4) => Q1R(4),
	Q(3) => Q1R(3),
	Q(2) => Q1R(2),
	Q(1) => Q1R(1),
	Q(0) => Q1R(0),
	C => CLK,
	CE => CEN1,
	CLR => R
);
L3 : REG16 port map(
	D(15) => D1I(15),
	D(14) => D1I(14),
	D(13) => D1I(13),
	D(12) => D1I(12),
	D(11) => D1I(11),
	D(10) => D1I(10),
	D(9) => D1I(9),
	D(8) => D1I(8),
	D(7) => D1I(7),
	D(6) => D1I(6),
	D(5) => D1I(5),
	D(4) => D1I(4),
	D(3) => D1I(3),
	D(2) => D1I(2),
	D(1) => D1I(1),
	D(0) => D1I(0),
	Q(15) => Q1I(15),
	Q(14) => Q1I(14),
	Q(13) => Q1I(13),
	Q(12) => Q1I(12),
	Q(11) => Q1I(11),
	Q(10) => Q1I(10),
	Q(9) => Q1I(9),
	Q(8) => Q1I(8),
	Q(7) => Q1I(7),
	Q(6) => Q1I(6),
	Q(5) => Q1I(5),
	Q(4) => Q1I(4),
	Q(3) => Q1I(3),
	Q(2) => Q1I(2),
	Q(1) => Q1I(1),
	Q(0) => Q1I(0),
	C => CLK,
	CE => CEN1,
	CLR => R
);

end SCHEMATIC;