z17w8.vhd

fast fourior transform

-- output of CoreGen module generator
-- $Header: delayVHT.vhd,v 1.3 1998/06/15 16:02:49 tonyw Exp $
-- ************************************************************************
--  Copyright 1996-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--  delay element
--  

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library xul;
use xul.ul_utils.all;

entity z17w8 is
  port( din :  in std_logic_vector( 8 -1 downto 0 );
        c   :  in std_logic;
        ce  :  in std_logic;
        dout:  out std_logic_vector( 8 - 1 downto 0 ));

end z17w8;

architecture behv of z17w8 is
  type data_array is array(17 downto 0) of 
                           std_logic_vector(8-1 downto 0);
  constant bus_width : integer := 8;
  constant clk_delay : integer := 17;

begin

 process
  variable setup  : boolean := TRUE;
  variable s      : data_array;
  variable vdin   : std_logic_vector( bus_width -1 downto 0 );
  variable vdout  : std_logic_vector( bus_width -1 downto 0 );
 begin

   if (setup = TRUE) then
     for i in clk_delay downto 0 loop
       s(i) := (OTHERS => '0');
     end loop;
     setup := FALSE;
   elsif (rat(c) = 'X' and rat(c'last_value) /= 'X' and rat(ce) /= '0') then
     for i in clk_delay downto 0 loop
       s(i) := (OTHERS => 'X');
     end loop;
   elsif (c'event and rat(c)='1' and rat(c'last_value)='0') then
     if (rat(ce) = 'X') then
       for i in clk_delay downto 0 loop
         s(i) := (OTHERS => 'X');
       end loop;
     elsif (rat(ce)='1') then
       vdin := std_logic_vector_2_var(din);
       for i in clk_delay-1 downto 0 loop
         s(i+1) := s(i);
       end loop;

       s(0) := vdin;
     end if;
   end if;
    
   vdout := s(clk_delay-1);
   dout <= vdout;

   wait on c;

 end process;

end behv;