reg16.vhd

fast fourior transform

-- output of CoreGen module generator
-- $Header: regceVHT.vhd,v 1.3 1998/06/15 17:53:00 tonyw Exp $
-- ************************************************************************
--  Copyright 1996-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--    Behaviorial simulation model for regsiters
--

library ieee;
-- use std.standard.all;
use ieee.std_logic_1164.all;
--  
library xul;
use xul.ul_utils.all;
--
ENTITY reg16 IS 
  PORT (d	: IN STD_LOGIC_VECTOR(16-1 DOWNTO 0);
        c	: IN STD_LOGIC;
        ce	: IN STD_LOGIC := default_fdce_ce;
        clr	: IN STD_LOGIC := default_fdce_clr;
        q	: OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END reg16;
--
-- behavior describing a parameterized LUT
ARCHITECTURE behv OF reg16 IS
--
CONSTANT bwid: INTEGER := 16;
CONSTANT rloc_x: rloctype := default_rloc;
CONSTANT rloc_y: rloctype := default_rloc;
CONSTANT userpm: rpmflagtype := default_userpm;
CONSTANT huset: husettype := default_huset;
--
BEGIN
-- 
-- Create CLB array except for the last clb
 PROCESS (c, clr)
 BEGIN
   IF (rat(clr) = 'X') THEN
     q <= setallX(bwid);
   ELSIF (rat(clr) = '1') THEN
     q <= setall0(bwid);
   ELSIF (rat(c) = 'X' AND rat(c'LAST_VALUE)/='X' AND rat(ce) /= '0') THEN
     q <= setallX(bwid);
   ELSIF (c'EVENT and rat(c) = '1' AND rat(c'LAST_VALUE) = '0') THEN
     IF (rat(ce) = 'X') THEN
       q <= setallX(bwid);
     ELSIF (rat(ce) = '1') THEN
       q <= d;
     END IF;
   END IF;
 END PROCESS;
--
END behv;