ramd1616.vhd

fast fourior transform

-- output of CoreGen module generator
-- $Header: syncramVHT.vhd,v 1.3 1998/06/15 16:22:07 tonyw Exp $
-- *****************************************************************
--  Copyright 1997-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--   Variable width/depth synchronous RAM
--

library ieee;
use ieee.std_logic_1164.all;
--  
library xul;
use xul.ul_utils.all;
--
ENTITY ramd1616 IS  
  PORT (a	: IN STD_LOGIC_VECTOR(4-1 DOWNTO 0);
        d	: IN STD_LOGIC_VECTOR(16-1 DOWNTO 0);
        we	: IN STD_LOGIC;
        c	: IN STD_LOGIC;
        ce	: IN STD_LOGIC := default_fdce_ce;
        q	: OUT STD_LOGIC_VECTOR(16-1 DOWNTO 0));
END ramd1616;
--
-- behavior describing a parameterized ram
ARCHITECTURE behv OF ramd1616 IS
--
CONSTANT width: INTEGER := 16;
CONSTANT depth: INTEGER := 16;
CONSTANT adrwid: INTEGER := 4;
CONSTANT rloc_x: rloctype := default_rloc;
CONSTANT rloc_y: rloctype := default_rloc;
CONSTANT userpm: rpmflagtype := default_userpm;
CONSTANT huset : husettype := default_huset;
CONSTANT memdata: memdatatype(0 TO 255):=
           (0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
            0,
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            0,
            0,
            0,
            0);
--
BEGIN
--
 PROCESS (c, ce, we, a)
 VARIABLE memdint : memdatatype(0 TO 255) := memdata;
 TYPE memtype IS ARRAY(0 TO 255) OF std_logic_vector(width-1 downto 0);
 VARIABLE memdvect : memtype;
 VARIABLE startup : BOOLEAN := TRUE;
 BEGIN
   IF (startup = TRUE) THEN
     q <= setall0(width);
     startup := FALSE;
     FOR i in 0 TO 255 LOOP
       memdvect(i) := int_2_std_logic_vector(memdint(i), width);
     END LOOP;
   ELSIF (rat(c) = 'X' and rat(c'last_value) /= 'X') THEN
     IF (rat(ce) /= '0') THEN
       q <= setallX(width);
     END IF;
     IF (rat(we) /= '0') THEN
         ASSERT FALSE
         REPORT "Memory Hazard: Clock is not defined when write enable is non-zero."
         SEVERITY WARNING;
       IF (anyX(a)) THEN
         FOR i IN 0 TO 255 LOOP
           memdvect(i) := setallX(width);
         END LOOP;
       ELSE
         memdvect(std_logic_vector_2_posint(a)) := setallX(width);
       END IF;
     END IF;
   ELSIF (c'EVENT and rat(c) = '1' AND rat(c'LAST_VALUE) = '0') THEN
     IF (rat(ce) = 'X') THEN
       q <= setallX(width);
     ELSIF (rat(ce) = '1') THEN
       IF (anyX(a)) THEN
         q <= setallX(width);
       ELSE
         q <= memdvect(std_logic_vector_2_posint(a));
       END IF;
     END IF;
     IF (rat(we) = 'X') THEN
       ASSERT FALSE
         REPORT "Memory Hazard: Write enable is not defined at the rising clock edge."
         SEVERITY WARNING;      
       IF (anyX(a)) THEN
         FOR i IN 0 TO 255 LOOP
           memdvect(i) := setallX(width);
         END LOOP;
       ELSE
         memdvect(std_logic_vector_2_posint(a)) := setallX(width);
       END IF;
     ELSIF (rat(we) = '1') THEN
       IF (anyX(a)) THEN
         ASSERT FALSE
           REPORT "Memory Hazard: Writing in a location when address is not defined."
           SEVERITY WARNING;      
         FOR i IN 0 TO 255 LOOP
           memdvect(i) := setallX(width);
         END LOOP;
       ELSE
         memdvect(std_logic_vector_2_posint(a)) := d;
       END IF;
     END IF;
   END IF;
 END PROCESS;
--
END behv;