tcompw16.vhd

fast fourior transform

-- output of CoreGen module generator
-- $Header: cmpsVHT.vhd,v 1.4 1998/06/17 18:34:23 dany Exp $
-- ************************************************************************
--  Copyright 1996-1998 - Xilinx, Inc.
--  All rights reserved.
-- ************************************************************************
--
--  Description:
--  ones/twos complementer
--  

library IEEE;
use IEEE.STD_LOGIC_1164.all;
library xul;
use xul.ul_utils.all;

entity tcompw16 is
  port( a:    in   std_logic_vector( 16 - 1 downto 0 );
        inv:  in   std_logic;
        c:    in   std_logic;
        ce:   in   std_logic;
        q:    out  std_logic_vector( 16 - 1 downto 0 ));
end tcompw16;

architecture behv of tcompw16 is
  constant k : integer := 16;
  CONSTANT two_comp : BOOLEAN := true;
begin

 process
   variable va   : std_logic_vector( k - 1 downto 0 );
   variable vq   : std_logic_vector( k - 1 downto 0 );
   VARIABLE one_detected : BOOLEAN := FALSE;
 begin

   va := std_logic_vector_2_var(a);

   -- ---------------------------------------------------------------------------- --
   -- If the clock is an X, and the clock enable is a 1 or an X, the output gets X --
   -- ---------------------------------------------------------------------------- --
   IF (rat(c)='X' AND rat(ce)/='0' AND rat(c'LAST_VALUE)/='X') THEN
     vq := (OTHERS => 'X');

   -- ---------------------------------------------------------------------------- --
   -- If the clock'event is valid then...                                          --
   -- ---------------------------------------------------------------------------- --
     ELSIF (c'EVENT and rat(c)='1' and rat(c'LAST_VALUE)='0') then

   -- ---------------------------------------------------------------------------- --
   -- If the clockenable is an X, the outputs get X                                --
   -- ---------------------------------------------------------------------------- --
       IF rat(ce)='X' THEN
         vq := (OTHERS => 'X');

   -- ---------------------------------------------------------------------------- --
   -- Otherwise, do the twos complement...                                         --
   -- ---------------------------------------------------------------------------- --
       ELSE IF rat(ce)='1' THEN
         IF two_comp THEN
           IF inv='1' THEN
             one_detected := FALSE;
             FOR i IN 0 TO k-1 LOOP
               IF one_detected THEN
                 vq(i) := NOT va(i);
               ELSE
                 vq(i) := va(i);
                 IF va(i)='1' THEN
                   one_detected := TRUE;
                 END IF;
               END IF;
             END LOOP;
           ELSIF inv='0' THEN
             vq := va;
           ELSE
             vq := (OTHERS => 'X');
           END IF;

   -- ---------------------------------------------------------------------------- --
   -- ...or the ones complement...                                                 --
   -- ---------------------------------------------------------------------------- --
         ELSE
           CASE inv IS
             WHEN '0' =>
               vq := va;
             WHEN '1' =>
               vq := NOT va;
             WHEN OTHERS => 
               vq := (OTHERS => 'X');
           END CASE;
         END IF;

         q <= vq;

       END IF;

     END IF;

   END IF;

   WAIT ON c;

 end process;

end behv;