ppc860sio.h

motorola mpc系列 mpc852cpu bsp

    int                 txBdNext;       /* next transmit BD to fill */
    int                 rxBdNext;       /* next receive BD to read */
    volatile SMC *      pSmc;           /* SMC parameter RAM. Must point */
					/* at DPRAM area for SMC1 or SMC2 */
    volatile SMC_REG *  pSmcReg;        /* SMC registers must point at */
					/* SMCMR1 or SMCMR2 */
    VINT32              intMask;        /* interrupt acknowledge mask */
    } SMC_DEV;

/* SCC device descriptor */

typedef struct          /* SCC_UART_DEV */
    {
    int 		sccNum;		/* number of SCC device */
    int 		txBdNum;	/* number of transmit buf descriptors */
    int 		rxBdNum;	/* number of receive buf descriptors */
    SCC_BUF * 		txBdBase;	/* transmit BD base address */
    SCC_BUF * 		rxBdBase;	/* receive BD base address */
    u_char * 		txBufBase;	/* transmit buffer base address */
    u_char *		rxBufBase;	/* receive buffer base address */
    VINT32 		txBufSize;	/* transmit buffer size */
    VINT32 		rxBufSize;	/* receive buffer size */
    int			txBdNext;	/* next transmit BD to fill */
    int			rxBdNext;	/* next receive BD to read */
    volatile SCC *	pScc;		/* SCC parameter RAM */
    volatile SCC_REG *	pSccReg;	/* SCC registers */
    VINT32		intMask;	/* interrupt acknowledge mask */
    } SCC_UART_DEV;

typedef struct          	/* I2C_PARAM */
    {				/* offset description */
    VINT16 	rbase;		/* 00 Rx buffer descriptors base address */
    VINT16 	tbase;		/* 02 Tx buffer descriptors base address */
    VINT8 	rfcr;		/* 04 Rx function code */
    VINT8 	tfcr;		/* 05 Tx function code */
    VINT16 	mrblr;		/* 06 maximum receive buffer length */
    VINT32 	ris;		/* 08 Rx internal state */
    VINT32 	ridp;		/* 0c Rx internal data pointer */
    VINT16 	rbptr;		/* 10 Rx buffer descriptor pointer */
    VINT16 	ribc;		/* 12 Rx internal byte count */
    VINT32 	rt;		/* 14 Rx temp */
    VINT32 	tis;		/* 18 Tx internal state */
    VINT32 	tidp;		/* 1c Tx internal data pointer */
    VINT16 	tbptr;		/* 20 Tx buffer descriptor pointer */
    VINT16 	tibc;		/* 22 Tx internal byte count */
    VINT32 	tt;		/* 24 Tx temp */
    VINT32 	notused;	/* 28 not used */
    VINT16 	rpbase;		/* 2c relocatable parameter RAM base */
    VINT16 	reserved;	/* 2e reserved */
    } I2C_PARAM;

/* standard dual-mode serial driver header structure follows      */

typedef struct ppc860_chan	/* PPC860SMC_CHAN */
    {
    /* always goes first */
    SIO_DRV_FUNCS	*pDrvFuncs;	/* driver functions */
    
    /* callbacks */

    STATUS	(*getTxChar)();	/* pointer to a xmitr function */
    STATUS	(*putRcvChar)();/* pointer to a recvr function */
    void *	getTxArg;
    void *	putRcvArg;

    VINT16              int_vec;        /* interrupt vector number */
    VINT16              channelMode;    /* SIO_MODE                */
    int                 baudRate;
    int                 clockRate;      /* CPU clock frequency (Hz) */
    int                 bgrNum;         /* number of BRG being used */
    VINT32 *            pBaud;          /* BRG registers */
    VINT32              regBase;        /* register/DPR base address */
    SMC_DEV             uart;           /* UART SCC device */
    } PPC860SMC_CHAN;


/* serial procedures */
IMPORT	void	ppc860DevInit		(PPC860SMC_CHAN *);
IMPORT	void	ppc860Int		(PPC860SMC_CHAN *);
IMPORT	void	ppc800DevInit		(PPC860SMC_CHAN *);
IMPORT	void	ppc800Int		(PPC860SMC_CHAN *);

/*  standard dual-mode serial driver header structure follows - SCC */

typedef struct ppc860Scc_chan	/* PPC860SCC_CHAN */
    {
    /* always goes first */

    SIO_DRV_FUNCS	*pDrvFuncs;	/* driver functions */
    
    /* callbacks */

    STATUS	(*getTxChar)();	/* pointer to a xmitr function */
    STATUS	(*putRcvChar)();/* pointer to a recvr function */
    void *	getTxArg;
    void *	putRcvArg;

    VINT16              int_vec;        /* interrupt vector number */
    VINT16              channelMode;    /* SIO_MODE                */
    int                 baudRate;
    int                 clockRate;      /* CPU clock frequency (Hz) */
    int                 bgrNum;         /* number of BRG being used */
    VINT32 *            pBaud;          /* BRG registers */
    VINT32              regBase;        /* register/DPR base address */
    SCC_UART_DEV        uart;           /* UART SCC device */
    } PPC860SCC_CHAN;

/* function declarations */

IMPORT	void	ppc860SccInt		(PPC860SCC_CHAN *);
IMPORT	void	ppc860SccDevInit	(PPC860SCC_CHAN *);

/* channels */

#define PPC860_CHANNEL_A	0
#define PPC860_CHANNEL_B	1

#define PPC860SMC_N_CHANS    2	/* number of serial channels on chip */

/* SIO -- mpc860 serial channel chip -- register definitions */

/* Buffer Descriptor Pointer Definitions */

/* Receive BD status bits 16-bit value */

#define BD_RX_EMPTY_BIT		0x8000	/* buffer is empty */
#define BD_RX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_RX_INTERRUPT_BIT	0x1000	/* set interrupt when filled */
#define BD_RX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_RX_IDLE_CLOSE_BIT	0x0100	/* Close on IDLE recv bit */
#define BD_RX_BREAK_CLOSE_BIT	0x0020	/* Close on break recv bit */
#define BD_RX_FRAME_CLOSE_BIT	0x0010	/* Close on frame error bit */
#define BD_RX_PARITY_ERROR_BIT	0x0008	/* Parity error in last byte */
#define BD_RX_OVERRUN_ERROR_BIT	0x0002	/* Overrun occurred */

/* Transmit BD status bits 16-bit value */

#define BD_TX_READY_BIT		0x8000	/* Transmit ready/busy bit */
#define BD_TX_WRAP_BIT		0x2000	/* last BD in chain */
#define BD_TX_INTERRUPT_BIT	0x1000	/* set interrupt when emptied */
#define BD_TX_CON_MODE_BIT	0x0200	/* Continuous Mode bit */
#define BD_TX_PREAMBLE_BIT	0x0100	/* send preamble sequence */

#define BD_STATUS_OFFSET	0x00	/* two bytes */
#define BD_DATA_LENGTH_OFFSET	0x02	/* two bytes */
#define	BD_BUF_POINTER_OFFSET	0x04	/* four bytes */

/*
 * MPC860 internal register/memory map (section 17 of prelim. spec)
 * note that these are offsets from the value stored in the IMMR
 * register, which is in the PowerPC special register address space
 * at register number 638
 */

/**** SIU module configuration ***/
#define MPC860_SIUMCR(base)	((VINT32 *) ((base) + 0x00))
/**** System Protection Control ***/
#define	MPC860_SYPCR(base)	((VINT32 *) ((base) + 0x04))
/**** SW watch dog timer value ***/
#define	MPC860_SWT(base)	((VINT32 *) ((base) + 0x08))
/*** Software service reg ***/
#define	MPC860_SWSR(base)	((VINT16 *) ((base) + 0x0E))
/*** Interrupt pending reg ***/
#define	MPC860_SIPEND(base)	((VINT32 *) ((base) + 0x10))
/*** Interrupt Mask reg ***/
#define	MPC860_SIMASK(base)	((VINT32 *) ((base) + 0x14))
/*** Interrupt Edge level mask ***/
#define	MPC860_SIEL(base)	((VINT32 *) ((base) + 0x18))
/*** Interrupt Vector reg ***/
#define	MPC860_SIVEC(base)	((VINT32 *) ((base) + 0x1C))
/*** Transfer error status ***/
#define	MPC860_TESR(base)	((VINT32 *) ((base) + 0x20))
/*** SDMA Config reg ***/
#define	MPC860_SDCR(base)	((VINT32 *) ((base) + 0x30))

/*** CP Interrupt vector reg ***/
#define	MPC860_CIVR(base)	((VINT16 *) ((base) + 0x930))
/*** CP Interrupt config reg ***/
#define	MPC860_CICR(base)	((VINT32 *) ((base) + 0x940))
/*** CP Interrupt pending reg ***/
#define	MPC860_CIPR(base)	((VINT32 *) ((base) + 0x944))
/*** CP Interrupt mask reg ***/
#define	MPC860_CIMR(base)	((VINT32 *) ((base) + 0x948))
/*** CP Interrupt in-service reg ***/
#define	MPC860_CISR(base)	((VINT32 *) ((base) + 0x94C))
/*** Port A data direction reg ***/
#define	MPC860_PADIR(base)	((VINT16 *) ((base) + 0x950))
/*** Port A pin assign reg ***/
#define	MPC860_PAPAR(base)	((VINT16 *) ((base) + 0x952))
/*** Port A open drain reg ***/
#define	MPC860_PAODR(base)	((VINT16 *) ((base) + 0x954))
/*** Port A data reg ***/
#define	MPC860_PADAT(base)	((VINT16 *) ((base) + 0x956))
/*** Port C data direction reg ***/
#define	MPC860_PCDIR(base)	((VINT16 *) ((base) + 0x960))
/*** Port C pin assign reg ***/
#define	MPC860_PCPAR(base)	((VINT16 *) ((base) + 0x962))
/*** Port C special options reg ***/
#define	MPC860_PCSO(base)	((VINT16 *) ((base) + 0x964))
/*** Port C data reg ***/
#define	MPC860_PCDAT(base)	((VINT16 *) ((base) + 0x966))
/*** Port C interrupt control reg ***/
#define	MPC860_PCINT(base)	((VINT16 *) ((base) + 0x968))
/*** Port D data direction reg ***/
#define	MPC860_PDDIR(base)	((VINT16 *) ((base) + 0x970))
/*** Port D pin assign reg ***/
#define	MPC860_PDPAR(base)	((VINT16 *) ((base) + 0x972))
/*** Port D data reg ***/
#define	MPC860_PDDAT(base)	((VINT16 *) ((base) + 0x976))

/*** Comm processor cmd reg ***/
#define	MPC860_CPCR(base)	((VINT16 *) ((base) + 0x9C0))
/*** RISC config reg ***/
#define	MPC860_RCCR(base)	((VINT16 *) ((base) + 0x9C4))
/*** RISC dev support status reg ***/
#define	MPC860_RMDS(base)	((VINT8  *) ((base) + 0x9C7))
/*** RISC ucode dev spt control reg ***/
#define	MPC860_RMDR(base)	((VINT32 *) ((base) + 0x9C8))
/*** RISC controller trap reg 1 ***/
#define	MPC860_RCTR1(base)	((VINT16 *) ((base) + 0x9CC))
/*** RISC controller trap reg 2 ***/
#define	MPC860_RCTR2(base)	((VINT16 *) ((base) + 0x9CE))
/*** RISC controller trap reg 3 ***/
#define	MPC860_RCTR3(base)	((VINT16 *) ((base) + 0x9D0))
/*** RISC controller trap reg 4 ***/
#define	MPC860_RCTR4(base)	((VINT16 *) ((base) + 0x9D2))
/*** RISC Timers event reg ***/
#define	MPC860_RTER(base)	((VINT16 *) ((base) + 0x9D6))
/*** RISC Timers mask reg ***/
#define	MPC860_RTMR(base)	((VINT16 *) ((base) + 0x9DA))

/*** baud rate generation register set ***/
/*** BRG1 configuration reg ***/
#define	MPC860_BRGC1(base)	((VINT32 *) ((base) + 0x9F0))
/*** BRG2 configuration reg ***/
#define	MPC860_BRGC2(base)	((VINT32 *) ((base) + 0x9F4))
/*** BRG3 configuration reg ***/
#define	MPC860_BRGC3(base)	((VINT32 *) ((base) + 0x9F8))
/*** BRG4 configuration reg ***/
#define	MPC860_BRGC4(base)	((VINT32 *) ((base) + 0x9FC))
/*** SCC1 Mode reg low ***/
#define	MPC860_GSMR_L1(base)	((VINT32 *) ((base) + 0xA00))
/*** SCC1 Mode reg High ***/
#define	MPC860_GSMR_H1(base)	((VINT32 *) ((base) + 0xA04))
/*** SCC1 Protocol Specific Mode reg ***/
#define	MPC860_PSMR1(base)	((VINT16 *) ((base) + 0xA08))
/*** SCC1 Transmit-On-Demand reg ***/
#define	MPC860_TODR1(base)	((VINT16 *) ((base) + 0xA0C))
/*** SCC1 Data Synchronization reg ***/
#define	MPC860_DSR1(base)	((VINT16 *) ((base) + 0xA0E))