📄 ppc860sio.h
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/************************************************************************
Copyright 2003 - 2004 UPTI, Inc.
filename : ppc860Sio.h
description : Motorola MPC800 SMC UART serial driver
author : lx
modification : lx create 2003-01-01
************************************************************************/
/*
* This file contains constants for the Motorola MPC860 PowerPC
* microcontroller chip.
*/
#ifndef __INCppc860Sioh
#define __INCppc860Sioh
#ifdef __cplusplus
extern "C" {
#endif
#ifndef _ASMLANGUAGE
#include "sioLib.h"
#include "drv/multi/ppc860Siu.h"
/* SCC Parameters */
typedef struct /* SCC_PARAM */
{ /* offset description*/
volatile INT16 rbase; /* 00 Rx buffer descriptor base address */
volatile INT16 tbase; /* 02 Tx buffer descriptor base address */
volatile INT8 rfcr; /* 04 Rx function code */
volatile INT8 tfcr; /* 05 Tx function code */
volatile INT16 mrblr; /* 06 maximum receive buffer length */
volatile INT32 rstate; /* 08 Rx internal state */
volatile INT32 res1; /* 0C Rx internal data pointer */
volatile INT16 rbptr; /* 10 Rx buffer descriptor pointer */
volatile INT16 res2; /* 12 reserved/internal */
volatile INT32 res3; /* 14 reserved/internal */
volatile INT32 tstate; /* 18 Tx internal state */
volatile INT32 res4; /* 1C reserved/internal */
volatile INT16 tbptr; /* 20 Tx buffer descriptor pointer */
volatile INT16 res5; /* 22 reserved/internal */
volatile INT32 res6; /* 24 reserved/internal */
volatile INT32 rcrc; /* 28 temp receive CRC */
volatile INT32 tcrc; /* 2C temp transmit CRC */
} SCC_PARAM;
typedef struct /* SCC_BUF */
{
volatile UINT16 statusMode; /* status and control */
UINT16 dataLength; /* length of data buffer in bytes */
u_char * dataPointer; /* points to data buffer */
} SCC_BUF;
typedef struct /* SCC */
{
SCC_PARAM param; /* SCC parameters */
char prot[64]; /* protocol specific area */
} SCC;
typedef struct /* SCC_REG */
{
UINT32 gsmrl; /* SCC general mode register - low */
UINT32 gsmrh; /* SCC eneral mode register - high */
UINT16 psmr; /* SCC protocol mode register */
UINT16 res1; /* reserved */
UINT16 todr; /* SCC transmit on demand */
UINT16 dsr; /* SCC data sync. register */
volatile UINT16 scce; /* SCC event register */
UINT16 res2; /* reserved */
UINT16 sccm; /* SCC mask register */
UINT8 res3; /* reserved */
volatile UINT8 sccs; /* SCC status register */
} SCC_REG;
/* device and channel structures */
/*
* The PPC860SMC_CHAN structure defines a serial I/O channel which
* describes the (TBD) registers for a given channel.
* Also the various SIO driver functions ( ioctl, txStarup, callbackInstall,
* pollInput, polloutput ) that this channel could utilize are declared
* here.
*/
/* roughly things copied in structure form from multi/m68360.h */
/* MPC860 Dual Ported Ram addresses */
#define PPC860_DPR_SCC1(dprbase) ((VINT32 *) ((dprbase) + 0x1c00))
#define PPC860_DPR_I2C(dprbase) ((VINT32 *) ((dprbase) + 0x1c80))
#define PPC860_DPR_MISC(dprbase) ((VINT32 *) ((dprbase) + 0x1cb0))
#define PPC860_DPR_IDMA1(dprbase) ((VINT32 *) ((dprbase) + 0x1cc0))
#define PPC860_DPR_SCC2(dprbase) ((VINT32 *) ((dprbase) + 0x1d00))
#define PPC860_DPR_SPI(dprbase) ((VINT32 *) ((dprbase) + 0x1d80))
#define PPC860_DPR_TMR(dprbase) ((VINT32 *) ((dprbase) + 0x1db0))
#define PPC860_DPR_IDMA2(dprbase) ((VINT32 *) ((dprbase) + 0x1dc0))
#define PPC860_DPR_SCC3(dprbase) ((VINT32 *) ((dprbase) + 0x1e00))
#define PPC860_DPR_SMC1(dprbase) ((VINT32 *) ((dprbase) + 0x1e80))
#define PPC860_DPR_DSP1(dprbase) ((VINT32 *) ((dprbase) + 0x1ec0))
#define PPC860_DPR_SCC4(dprbase) ((VINT32 *) ((dprbase) + 0x1f00))
#define PPC860_DPR_SMC2(dprbase) ((VINT32 *) ((dprbase) + 0x1f80))
#define PPC860_DPR_DSP2(dprbase) ((VINT32 *) ((dprbase) + 0x1fc0))
/*
* dual-ported parameter RAM SMC offsets
* access these with SMC_RBASE(base_dpram_addr_of_this_SMC1)
* base_dpram_addr_of_this_SMC1 == PPC860_DPR_SMC1(dprbase)
* or == PPC860_DPR_SMC2(dprbase)
*/
#define SMC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SMC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SMC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
#define SMC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
#define SMC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SMC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SMC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SMC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SMC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SMC_MAX_IDL(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SMC_IDLC(base) ((VINT16 *) ((base) + 0x2A)) /* Temp Idle counter */
#define SMC_BRKLN(base) ((VINT16 *) ((base) + 0x2C)) /* Last Rx Break length*/
#define SMC_BRKEC(base) ((VINT16 *) ((base) + 0x2E)) /* Rx Brk Cond counter */
#define SMC_BRKCR(base) ((VINT16 *) ((base) + 0x30)) /* Break Count reg (Tx)*/
#define SMC_RMASK(base) ((VINT16 *) ((base) + 0x32)) /* Temp bit mask */
/* dual ported parameter RAM PIP offsets */
#define PIP_RBASE(base) ((VINT16 *)((base) + 0x00)) /* Rx Buff Descr Base */
#define PIP_TBASE(base) ((VINT16 *)((base) + 0x01)) /* Tx Buff Descr Base */
#define PIP_CFCR(base) ((VINT8 *)((base) + 0x04)) /* Cent. Function Code */
#define PIP_SMASK(base) ((VINT8 *)((base) + 0x05)) /* Status mask */
/*
* dual-ported parameter RAM SCC offsets
* access these with SCC_RBASE(base_dpram_addr_of_this_SCC1)
* base_dpram_addr_of_this_SCC1 == PPC860_DPR_SCC1(dprbase)
* or == PPC860_DPR_SCC1(dprbase)
*/
#define SCC_RBASE(base) ((VINT16 *) ((base) + 0x00)) /* Rx Buff Descr Base */
#define SCC_TBASE(base) ((VINT16 *) ((base) + 0x02)) /* Tx Buff Descr Base */
#define SCC_RFCR(base) ((VINT8 *) ((base) + 0x04)) /* Rx Function Code */
#define SCC_TFCR(base) ((VINT8 *) ((base) + 0x05)) /* Tx Function Code */
#define SCC_MRBLR(base) ((VINT16 *) ((base) + 0x06)) /* Max Rcv Buff Length */
#define SCC_RSTATE(base) ((VINT32 *) ((base) + 0x08)) /* Rx Internal State */
#define SCC_RBPTR(base) ((VINT16 *) ((base) + 0x10)) /* Rx Buffer Pointer */
#define SCC_TSTATE(base) ((VINT32 *) ((base) + 0x18)) /* Tx Internal State */
#define SCC_TBPTR(base) ((VINT16 *) ((base) + 0x20)) /* Tx Buffer Pointer */
#define SCC_RCRC(base) ((VINT16 *) ((base) + 0x28)) /* Max Idle characters */
#define SCC_TCRC(base) ((VINT16 *) ((base) + 0x2C)) /* Max Idle characters */
/* UART mode */
#define SCC_MAX_IDL(base) ((VINT16 *) ((base) + 0x38)) /* Max Idle characters */
#define SCC_IDLC(base) ((VINT16 *) ((base) + 0x3A)) /* Temp Idle counter */
#define SCC_BRKCR(base) ((VINT16 *) ((base) + 0x3C)) /* Break Count Reg (Tx)*/
#define SCC_PAREC(base) ((VINT16 *) ((base) + 0x3E)) /* Rx Parity Err Cnt */
#define SCC_FRMEC(base) ((VINT16 *) ((base) + 0x40)) /* Rx Frame Err Cnt */
#define SCC_NOSEC(base) ((VINT16 *) ((base) + 0x42)) /* Receive Noise Cnt */
/* HDLC mode */
#define HDLC_C_MASK(base) ((VINT32 *) ((base) + 0x34)) /* CRC mask.32bit: 0xDEBB20E3,16bit: 0x0000F0B8*/
#define HDLC_C_PRES(base) ((VINT32 *) ((base) + 0x38)) /* CRC preset */
#define HDLC_DISFC(base) ((VINT32 *) ((base) + 0x3c)) /* Discard frame counter */
#define HDLC_CRCEC(base) ((VINT16 *) ((base) + 0x3e)) /* CRC error frame counter */
#define HDLC_ABTSC(base) ((VINT16 *) ((base) + 0x40)) /* Abort sequence counter */
#define HDLC_NMARC(base) ((VINT16 *) ((base) + 0x42)) /* Nonmatching address received counter */
#define HDLC_RETRC(base) ((VINT16 *) ((base) + 0x44)) /* Frame retransmation counter */
#define HDLC_MFLR(base) ((VINT16 *) ((base) + 0x46)) /* Max frame length register */
#define HDLC_MAX_CNT(base) ((VINT16 *) ((base) + 0x48)) /* Maxinum length counter */
#define HDLC_RFTHR(base) ((VINT16 *) ((base) + 0x4A)) /* Receive frames threshold */
#define HDLC_RFCNT(base) ((VINT16 *) ((base) + 0x4C)) /* Receive frames counter */
#define HDLC_HMASK(base) ((VINT16 *) ((base) + 0x4E)) /* Mask register */
#define HDLC_HADDR1(base) ((VINT16 *) ((base) + 0x50)) /* Address register */
#define HDLC_HADDR2(base) ((VINT16 *) ((base) + 0x52)) /* Address register */
#define HDLC_HADDR3(base) ((VINT16 *) ((base) + 0x54)) /* Address register */
#define HDLC_HADDR4(base) ((VINT16 *) ((base) + 0x56)) /* Address register */
#define HDLC_TMP(base) ((VINT16 *) ((base) + 0x58)) /* Temp */
#define HDLC_TMP_MB(base) ((VINT16 *) ((base) + 0x5A)) /* Temp */
/*
* dual-ported parameter RAM I2C offsets
* access these with I2C_RPBASE(base_dpram_addr_of_I2C)
*/
#define I2C_RPBASE(base) ((VINT16 *) ((char *)base + 0x2C))
typedef struct /* SMC_BUF */
{
VUINT16 statusMode; /* status and control */
VINT16 dataLength; /* length of data buffer in bytes */
u_char * dataPointer; /* points to data buffer */
} SMC_BUF;
typedef struct /* SMC_PARAM */
{ /* offset description*/
VINT16 rbase; /* 00 Rx buffer descriptor base address */
VINT16 tbase; /* 02 Tx buffer descriptor base address */
VINT8 rfcr; /* 04 Rx function code */
VINT8 tfcr; /* 05 Tx function code */
VINT16 mrblr; /* 06 maximum receive buffer length */
VINT32 rstate; /* 08 Rx internal state */
VINT32 res1; /* 0C Rx internal data pointer */
VINT16 rbptr; /* 10 Rx buffer descriptor pointer */
VINT16 res2; /* 12 reserved/internal */
VINT32 res3; /* 14 reserved/internal */
VINT32 tstate; /* 18 Tx internal state */
VINT32 res4; /* 1C reserved/internal */
VINT16 tbptr; /* 20 Tx buffer descriptor pointer */
VINT16 res5; /* 22 reserved/internal */
VINT32 res6; /* 24 reserved/internal */
VINT16 maxidl; /* 28 Maximum idle characters */
VINT16 idlc; /* 2A temporary idle counter */
VINT16 brkln; /* 2C last recv break length */
VINT16 brkec; /* 2E recv break condition counter */
VINT16 brkcr; /* 30 xmit break count register */
VINT16 r_mask; /* 32 temporary bit mask */
} SMC_PARAM;
typedef struct /* SMC */
{
SMC_PARAM param; /* SMC parameters */
} SMC;
typedef struct /* SMC_REG */
{
VINT16 smcmr; /* SMC Mode register */
VINT8 res1[2]; /* reserved */
VINT8 smce; /* SMC Event register */
VINT8 res2[3]; /* reserved */
VINT8 smcm; /* SMC Mask register */
} SMC_REG;
/* SMC device descriptor */
typedef struct /* SMC_DEV */
{
int smcNum; /* number of SMC device (1 or 2)*/
int txBdNum; /* number of transmit buf descriptors */
int rxBdNum; /* number of receive buf descriptors */
SMC_BUF * txBdBase; /* transmit BD base address */
SMC_BUF * rxBdBase; /* receive BD base address */
u_char * txBufBase; /* transmit buffer base address */
u_char * rxBufBase; /* receive buffer base address */
VINT32 txBufSize; /* transmit buffer size */
VINT32 rxBufSize; /* receive buffer size */
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