drv_852smc.h

motorola mpc系列 mpc852cpu bsp

#ifndef _DRV_852SMC_H_
#define _DRV_852SMC_H_


#define M852_SMCMR1(base)          (CAST(VUINT16*)((base) + 0x00a82))
#define M852_SMCMR2(base)          (CAST(VUINT16*)((base) + 0x00a92))
#define	M852_SMCE1(base)	       (CAST(VUINT8 *) ((base) + 0x0A86)) /* SMC1 Event Reg */
#define	M852_SMCM1(base)	       (CAST(VUINT8 *) ((base) + 0x0A8A)) /* SMC1 Mask Reg */


#include "Typedef.h"
_U32 Drv_Print(const char *pStr, ...);
#pragma pack(1)
typedef struct
{
    _U16    RBASE;                  /*offset:00*/
    _U16    TBASE;                  /*offset:02*/
    _U8     RFCR;                   /*offset:04*/
    _U8     TFCR;                   /*offset:05*/
    _U16    MRBLR;                  /*offset:06*/
    _U32    RSTATE;                 /*offset:08*/
    _U32    RSV1;                   /*offset:0C*/
    _U16    RBPTR;                  /*offset:10*/
    _U16    RSV2;                   /*offset:12*/
    _U32    RSV3;                   /*offset:14*/
    _U32    TSTATE;                 /*offset:18*/
    _U32    RSV4;                   /*offset:1C*/
    _U16    TBPTR;                  /*offset:20*/
    _U16    RSV5;                   /*offset:22*/
    _U32    RSV6;                   /*offset:24*/
    _U16    MAX_IDL;                /*offset:28*/
    _U16    IDLC;                   /*offset:2A*/
    _U16    BRKLN;                  /*offset:2C*/
    _U16    BRKEC;                  /*offset:2E*/
    _U16    BRKCR;                  /*offset:30*/
    _U16    R_MASK;                 /*offset:32*/
}SMC_UART_PARAM_RAM;
#pragma pack()

typedef struct SmcBufferDescriptor
{
    unsigned short bd_cstatus;     /* control and status */
    unsigned short bd_length;      /* transfer length */
    unsigned char  *bd_addr;       /* buffer address */
} SerBD;

/* Receive BD status bits 16-bit value */

#define SMC_UART_RXBD_EMPTY_BIT            0x8000     /* buffer is empty */
#define SMC_UART_RXBD_WRAP_BIT             0x2000     /* last BD in chain */
#define SMC_UART_RXBD_INT_BIT              0x1000     /* set interrupt when filled */
#define SMC_UART_RXBD_CON_MODE_BIT         0x0200     /* Continuous Mode bit */
#define SMC_UART_RXBD_IDLE_CLOSE_BIT       0x0100     /* Close on IDLE recv bit */
#define SMC_UART_RXBD_BREAK_CLOSE_BIT      0x0020     /* Close on break recv bit */
#define SMC_UART_RXBD_FRAME_CLOSE_BIT      0x0010     /* Close on frame error bit */
#define SMC_UART_RXBD_PARITY_ERROR_BIT     0x0008     /* Parity error in last byte */
#define SMC_UART_RXBD_OVERRUN_ERROR_BIT    0x0002     /* Overrun occurred */

/* Transmit BD status bits 16-bit value */

#define SMC_UART_TXBD_READY_BIT           0x8000      /* Transmit ready/busy bit */
#define SMC_UART_TXBD_WRAP_BIT            0x2000      /* last BD in chain */
#define SMC_UART_TXBD_INTERRUPT_BIT       0x1000      /* set interrupt when emptied */
#define SMC_UART_TXBD_CON_MODE_BIT        0x0200      /* Continuous Mode bit */
#define SMC_UART_TXBD_PREAMBLE_BIT        0x0100      /* send preamble sequence */


#define PB20                        0x00000800
#define PB21                        0x00000400
#define PB24                        0x00000080
#define PB25                        0x00000040

#define DRV_SMC_TX_ENABLE           0x0002
#define DRV_SMC_RX_ENABLE           0x0001

#define DRV_SMC_TX_MAX_WAIT_COUNT   0x00080000
#define DRV_SMC_RX_MAX_WAIT_COUNT   0x00000000  /*不等待*/

#define DRV_SMC_SDCR_RAID_BR5	    0x00000001	/* U-BUS arbitration priority 5 (BR5) */


#define DRV_SMC1_SIMODE_NMSI        0x00000000    /* NMSI mode */
#define DRV_SMC1_SIMODE_CS_BRG3     0x00002000    /* BRG3 is clock source */


/*
GSMR_L(TDCR/RDCR == 10) /16   BRGC(DIV16 == 0 ) /1
*/
#define BAUD_RATE_VALUE(baudrate)   ( (BRGCLK_FREQ /(16*baudrate)) - 1 )


#if SMC_TXINT

enum
{
    SMC1_IDLE,
    SMC1_BUSY
};

enum
{
    SMC_IDLE,
    SMC_BUSY
};

#define SMC1_SEND_BUFF_LEN      4096
#define SMC1_RECV_BUFF_LEN      64


#define IV_SMC1			        (36)	/* SMC 1 */

#define CISR_SMC1                0x00000010
#define CIPR_SMC1                0x00000010
#define CIMR_SMC1                0x00000010


typedef struct
{
/*	_U8  ucSmcSendBuff[SMC_SEND_BUFF_LEN];*/
	_U8  *ucSmcSendBuff;
	_U32 ulSmcSendHead;
	_U32 ulSmcSendTail;
	_U8  ucSmcSendStatus;

    _U32 ulSmcIntFlag;
    _U32 ulSmcLastTick;

    _U32 ulSmcAbnormity; /*发送异常*/

/*	_U8  ucSmcRecvBuff[SMC_RECV_BUFF_LEN];*/
	_U8  *ucSmcRecvBuff;
	_U32 ulSmcRecvHead;
	_U32 ulSmcRecvTail;
	_U8  ucSmcRecvStatus;

	_U32 ulSmcInt;
	_U32 ulSmcRxInt;
	_U32 ulSmcTxInt;
	_U32 ulSmcBSYInt;
	_U32 ulSmcBRKInt;
	_U32 ulSmcBRKEInt;

	_U32 ulTxFailTimes;
	_U32 ulTxLen;
}STSMCPARA;

typedef struct
{
	_U8*    ucSmc1SendBuff;
	_U32    ulSmc1SendHead;
	_U32    ulSmc1SendTail;
	_U8     ucSmc1SendStatus;

    _U32    ulSmcIntFlag;
    _U32    ulSmcLastTick;

    _U32    ulSmcAbnormity; /*发送异常*/

	_U8*    ucSmc1RecvBuff;
	_U32    ulSmc1RecvHead;
	_U32    ulSmc1RecvTail;
	_U8     ucSmc1RecvStatus;

	_U32    ulSmcInt;
	_U32    ulSmcRxInt;
	_U32    ulSmcTxInt;
	_U32    ulSmcBSYInt;
	_U32    ulSmcBRKInt;
	_U32    ulSmcBRKEInt;

	_U32    ulTxFailTimes;
	_U32    ulTxLen;
}STSMC1PARA;
#endif

extern UINT32 vxImmrGet (void);
_U32 Drv_SmcCreate( _U8 u8Type,_U32 u32Channel );
_U32 Drv_Print(const char *pStr, ...);
void InChar ( unsigned char *szString, unsigned long *ret );
void LoadCtrl_Receive(char *pString, _U32 MaxLength);

#endif