rominit.s

motorola mpc系列 mpc852cpu bsp

/************************************************************************
Copyright 2003 - 2004 UPTI.

filename     : romInit.s

description  : Motorola 866ads ROM initialization module

author       : young

modification : young   create            2004-09-17
************************************************************************/


    .data
    .globl  copyright_wind_river
    .long   copyright_wind_river

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

*/

#define     _ASMLANGUAGE

#define     DEV_TG              1
#define     DEV_AG              2
#define     DEV_HPBX            3
#define     DEV_852T            4


#include "vxWorks.h"
#include "asm.h"
#include "cacheLib.h"
#include "config.h"
#include "regs.h"
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"

#define EQUIP_TEST          0
#define BOOTROM_VERSION     1

/* internals */
.globl    _romInit    /* start of system code */
.globl    romInit        /* start of system code */
.globl    LedCtrl
.globl    LedDBTest

/* externals */
.extern   romStart    /* system initialization routine */
.extern   LedCtrl
.extern   LedDBTest

.text
.align    2

/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*

* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )

*/

_romInit:
romInit:

    bl      cold            /* jump to the cold boot initialization */

    bl      start           /* jump to the warm boot initialization */

    /* copyright notice appears at beginning of ROM (in TEXT segment) */
    .long    BOOTROM_VERSION
    .ascii   "Copyright 2005-2006 kztech Systems, Inc."
    .align   2

cold:

    li      r3, BOOT_COLD               /* set cold boot as start type */

    /*
     * When the PowerPC 860 is powered on, the processor fetch the
     * instructions located at the address 0x100. We need to jump
     * from the address 0x100 to the Flash space.
     */

    lis     r4, HIADJ(start)            /* load r4 with the address */
    addi    r4, r4, LO(start)           /* of start */

    lis     r5, HIADJ(romInit)          /* load r5 with the address */
    addi    r5, r5, LO(romInit)         /* of romInit() */

    lis     r6, HIADJ(ROM_TEXT_ADRS)    /* load r6 with the address */
    addi    r6, r6, LO(ROM_TEXT_ADRS)   /* of ROM_TEXT_ADRS */

    sub     r4, r4, r5                  /* r4 - r5 + r6 */
    add     r4, r4, r6                  /* jump to start-romInit+ROM_TEXT_ADRS*/

    mtspr   LR, r4                      /* save destination address*/
                                        /* into LR register */
    blr                                 /* jump to flash mem address */


start:
    /* set the MSR register to a known state
       See 866um.pdf 4.1.2.3.1
    */
    xor     r4, r4, r4                  /* clear register R4 */
    mtmsr   r4                          /* clear the MSR register */


    /* DER - clear the Debug Enable Register
       See 866um.pdf 45.5.2.2
    */
    mtspr    DER, r4


    /* ICR - clear the Interrupt Cause Register
       See 866um.pdf 45.5.2.1
    */
    mtspr   ICR, r4

    /*
     * ICTRL - initialize the Intstruction Support Control register
     * Set ISCT_SER=111,Core is not serialized(normal mode); no show
     * cycle is performed for fetched instructions.
     * See 866um.pdf 45.5.1.3
     */

    lis     r5, HIADJ(0x00000007)
    addi    r5, r5, LO(0x00000007)
    mtspr   ICTRL, r5



    /* disable the instruction/data cache
     * See 866um.pdf 7.3.1 and 7.3.2
     */

    lis     r4, HIADJ ( CACHE_CMD_DISABLE)      /* load disable cmd */
    addi    r4, r4, LO (CACHE_CMD_DISABLE)
    mtspr   IC_CST, r4                          /* disable I cache */
    mtspr   DC_CST, r4                          /* disable D cache */

    /* unlock the instruction/data cache */

    lis     r4, HIADJ ( CACHE_CMD_UNLOCK_ALL)   /* load unlock cmd */
    addi    r4, r4, LO (CACHE_CMD_UNLOCK_ALL)
    mtspr   IC_CST, r4              /* unlock all I cache lines */
    mtspr   DC_CST, r4              /* unlock all D cache lines */

    /* invalidate the instruction/data cache */

    lis     r4, HIADJ (CACHE_CMD_INVALIDATE)    /* load invalidate cmd*/
    addi    r4, r4, LO (CACHE_CMD_INVALIDATE)
    mtspr   IC_CST, r4              /* invalidate all I cache lines */
    mtspr   DC_CST, r4              /* invalidate all D cache lines */


    /*
     * initialize the IMMR register before any non-core registers
     * modification.
     * see 866um.pdf 10.4.1
     */

    lis     r4, HIADJ( INTERNAL_MEM_MAP_ADDR)
    addi    r4, r4, LO(INTERNAL_MEM_MAP_ADDR)
    mtspr   IMMR, r4                /* initialize the IMMR register */

    mfspr   r4, IMMR                /* read it back, to be sure */
    rlwinm  r4, r4, 0, 0, 15        /* only high 16 bits count */

    /* SYPCR -System Protection Control Register
     *        turn off the system protection stuff
     * see 866um.pdf 10.4.3
     * 配置看门狗、总线监控:禁止掉866内部看门狗
     */
    lis     r5, HIADJ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF )
    addi    r5, r5, LO( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF )
    stw     r5, SYPCR(0)(r4)


    /* set the SIUMCR register for important debug port, etc... stuff
     * see 866um.pdf 10.4.2
     */
    /*lis     r6, HIADJ( SIUMCR_FRC | SIUMCR_DLK  | SIUMCR_DPC | \
               SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
    addi    r6, r6, LO(SIUMCR_FRC | SIUMCR_DLK  | SIUMCR_DPC | \
               SIUMCR_MLRC_3STATES | SIUMCR_AEME | SIUMCR_GB5E)
    */
    lwz     r5, SIUMCR(0)(r4)
    lis     r6, HIADJ( 0x00032400 )         /* set IR6 */
    addi    r6, r6, LO( 0x00032400 )
    or      r5, r5, r6
    stw     r5, SIUMCR(0)(r4)


    /* TBSCR - initialize the Time Base Status and Control register
     * see 866um.pdf 10.9.3
     * 清除参考值中断
     */
    lis     r5, HIADJ( TBSCR_REFA | TBSCR_REFB)
    addi    r5, r5, LO(TBSCR_REFA | TBSCR_REFB)
    sth     r5, TBSCR(0)(r4)

    /* set PIT status and control init value
     * see 866um.pdf 10.11.1
     * 清循环中断
     */
    li      r5, PISCR_PS | PISCR_PITF
    sth     r5, PISCR(0)(r4)


    /* set the SPLL frequency
     * see 866um.pdf 14.6.2
     * 初始化锁相环
     */
	/*     
    	lis     r5, HIADJ( (SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
                                PLPRCR_TEXPS)
    	addi    r5, r5, LO((SPLL_MUL_FACTOR << PLPRCR_MF_SHIFT) | \
                                PLPRCR_TEXPS)
	*/                                


    	lis     r5, HIADJ(0x00184006)
    	addi    r5, r5, LO(0x00184006)
    	stw     r5, PLPRCR(0)(r4)



    /*
     * Map the bank 0 to the flash area - On the ADS board at reset time
     * the bank 0 is already used to map the flash.
     * about the BR OR see 15.4.1 15.4.2
     *
     * cs0配置为bios，缺省有效 */
    /* BA = 0x0c00, AT = 0, PS = 01 8位port size, PARE = 0,
     * MS = 00 GPCM, Valid = 1 有效
     */
    lis     r5, HIADJ( (ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_8 | BR_V)
    addi    r5, r5, LO((ROM_BASE_ADRS & BR_BA_MSK) | BR_PS_8 | BR_V)
    stw     r5, BR0(0)(r4)
    /* AM = 0xFFF8, ATM = 00, CSNT = 1, ACS = 00, BI = 1 不支持burst访问
     * SCY = 1111 15 clock cycle, SETA = 0, TRLX = 1 timing relaxed, EHTR = 0.
     */
    lis     r5, HIADJ( 0xFFF80000 | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
    addi    r5, r5, LO(0xFFF80000 | OR_CSNT_SAM | OR_BI | OR_SCY_15_CLK | OR_TRLX)
    stw     r5, OR0(0)(r4)

    /*************************************************************************
     SDRAM初始化顺序:
        1、write ram array;
        2、program MPTPR;
        3、program MAMR/MBMR;
        4、setup BRx ORx.
        内存共64M，cs1分给第一个bank(32M),cs2分给第二个bank(32M)
    *************************************************************************/

    /* 1、write ram array */

    /* load r6/r7 with the start/end address of the UPM table. */

    lis     r6, HIADJ( upmaTableSdram)
    addi    r6, r6, LO(upmaTableSdram)
    lis     r7, HIADJ( upmaTableSdramEnd)
    addi    r7, r7, LO(upmaTableSdramEnd)

    /* init UPMA for memory access */

    sub     r5, r7, r6              /* compute table size */
    srawi   r5, r5, 2               /* in integer size */

    /* convert UpmTable to ROM based addressing */

    lis     r7, HIADJ(romInit)
    addi    r7, r7, LO(romInit)

    lis     r8, HIADJ(ROM_TEXT_ADRS)
    addi    r8, r8, LO(ROM_TEXT_ADRS)