config.h

motorola mpc系列 mpc852cpu bsp

/* ads860/config.h - Motorola 860ads board configuration header */

/* Copyright 1984-1997 Wind River Systems, Inc. */

/*
modification history
--------------------
01t,04mar99,cn   merge from ads860 release view, defaults to INCLUDE_END
		 (SPR# 23153).
01s,09feb99,cn   added macro NV_RAM_SIZE (SPR# 23387), also added support 
		 for SDRAM (SPR# 24337).
01r,18nov98,cn   END drivers are not selected for default.
01q,09nov98,cn   added support for 860T boards and FEC.
		 Changed ROM_SIZE to be 2Meg as in Makefile (SPR# 22572).
01p,08oct98,ms   made #define INCLUDE_CPM conditional on INCLUDE_NETWORK
01o,22jun98,cn   added support for Enhanced Network Driver.
01n,10jul98,sut  changed BSP_VERSION to "1.2" and BSP_REV to "/0"
                 added BSP_VER_1_2 macro ( Tornado 2.0 release ).
01m,28apr98,yp   added support for TFFS.
01l,08apr98,gls  BSP_REV level 3, for re-release to support FADS
01k,11nov97,map  added definitions for SYS_AUX_CLK [SPR# 9366].
01j,21feb97,mas  added undef of INCLUDE_TIMESTAMP (SPR 7879).
01i,03jan97,dat  BSP_REV level 2, for tornado 1.0.1 release
01h,12nov96,tam  added DEFAULT_POWER_MGT_MODE to select the default power
		 management mode.
01g,11nov96,tpr  turned the cache off when EDO dran selected.
01f,10nov96,tpr  defined cache and MMU support.
		 replaced SYS_CLK_FREQ by SPLL_FREQ_REQUESTED.
01e,08nov96,tpr  removed CPU_SPEED.
01d,06nov96,tpr  changed RAM_LOW_ADRS to 0x00010000.
01c,06nov96,tpr  increased BSP_REV from 0 to 1.
		 + added CLK macros.
01b,28may96,dzb  added Ethernet driver defines.
01a,19apr96,tpr  written.
*/

/*
This file contains the configuration parameters for the
Motorola MPC860ADS board.
*/

#ifndef	INCconfigh
#define	INCconfigh

/* BSP version/revision identification, should be placed
 * before #include "configAll.h"
 */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
/* 版本号 */
#define BSP_VERSION     "2.0.0.2"
#define BSP_REV         "/0"        /* 0 for the first bsp revision */

#include "configAll.h"

#undef FADS_860T		/* define it in the case of a FADS860T */
#define FADS_860T		/* define it in the case of a FADS860T */

/* remove unnecessary drivers */
#undef  INCLUDE_SM_NET
#undef  INCLUDE_SM_SEQ_ADDR

#undef     INCLUDE_Z85230_SIO

#undef     INCLUDE_ATA          /* ATA-2 portion of EIDE support */
#undef      INCLUDE_FD          /* [OPTIONAL] Floppy Disk  */

/* HSI Transparent Mode Driver Option (#define / #undef) */
#undef INCLUDE_HSI_TMD

/* HSI BackEnd Option  (#define / #undef) */
#undef INCLUDE_HSI_BACKEND

#define FORCE_DEFAULT_BOOT_LINE

#ifdef FADS_860T
#define DEFAULT_BOOT_LINE \
"motfec(0,0):vxWorks h=10.3.16.20 e=10.3.16.48:FFFFFF00 u=ap pw=ap o=motfec"
#else /* FADS_860T */
#define DEFAULT_BOOT_LINE \
"cpm(0,0):vxWorks  h=10.3.16.20 e=10.3.16.48:FFFFFF00 u=ap pw=ap o=cpm"
#endif /* FADS_860T */

/* DRAM type on the ADS board */

#undef INCLUDE_WDB

/* Cache and MMU not supported */
/*
 * Cache configuration
 * Note that when MMU is enabled, cache modes are controlled by
 * the MMU table entries in sysPhysMemDesc[], not the cache mode
 * macros defined here.
 */

#define     INCLUDE_CACHE_SUPPORT


/* Caches/MMU Options */
#define USER_I_CACHE_ENABLE
#define USER_D_CACHE_ENABLE
#undef  INCLUDE_CACHE_L2

/* Transparent Mode Driver requires Write-Through */
#if     defined(INCLUDE_EST_TM) || defined(INCLUDE_EST_VIO)
#undef     USER_D_CACHE_MODE
#define     USER_D_CACHE_MODE   CACHE_WRITETHROUGH
#else
#undef     USER_D_CACHE_MODE
#define     USER_D_CACHE_MODE   (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)
#endif


/* MMU Options */
#define     INCLUDE_MMU_BASIC       /* bundled mmu support */
#define USER_I_MMU_ENABLE
#define USER_D_MMU_ENABLE

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
  #define INCLUDE_MMU
#endif

#define INCLUDE_NETWORK



/* Number of TTY definition */
#define USE_SMC1                1
#undef USE_SMC2                

#undef	NUM_TTY
#define	NUM_TTY		N_SIO_CHANNELS		/* defined in ads860.h */

/* Optional timestamp support */

#undef  INCLUDE_TIMESTAMP

/* optional TrueFFS support */

#undef INCLUDE_TFFS

#ifdef INCLUDE_TFFS
#define  INCLUDE_TFFS_BOOT_IMAGE          /* for boot block */
#define  INCLUDE_TL_FTL              /* NOR based flash */
#define  INCLUDE_MTD_CFISCS          /* CFI/SCS for 8245 Intel part */
#define INCLUDE_MTD_AMD               /* AMD for 8240 AMD array */
#endif


#ifdef INCLUDE_TFFS
#define INCLUDE_DOSFS		/* dosFs file system */
#define INCLUDE_SHOW_ROUTINES	/* show routines for system facilities*/
#endif /* INCLUDE_DOSFS */

#define DEFAULT_IMMR_ADRS        (_U32)0xFFF00000
/* clock rates */

#define	SYS_CLK_RATE_MIN	1	/* minimum system clock rate */
#define	SYS_CLK_RATE_MAX	8000	/* maximum system clock rate */
#define	AUX_CLK_RATE_MIN	1	/* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX	8000	/* maximum auxiliary clock rate */

/*
 * Cristal Frequency - This macro defines the input oscillator frequency
 * clocking the PPC860. On the ADS board, the CPU is clocked by a cristal
 * running at 4 Mhz.
 */

#define CRISTAL_FREQ            FREQ_50_MHZ         /* 50 Mhz */

/*
 * SPLL_FREQ_REQUESTED - This macro defined the expected system PLL (SPLL)
 * frequency divided by 2. The two supported frequencies are either 25
 * or 50 MHz. Use 50Mhz in the case of a FADS860T board.
 */


#define SPLL_FREQ_REQUESTED	FREQ_50_MHZ		/* 50 Mhz */


/*
 * DRAM refresh frequency - This macro defines the DRAM refresh frequency.
 * e.i: A DRAM with 1024 rows to refresh in 16ms: 
 * DRAM_REFRESH_FREQ = 1024/ 16E-3 = 64E3 hz
 */

#define DRAM_REFRESH_FREQ	64000			/* 64 kHz */


/*
 * Baud Rate Generator division factor - 0 for division by 1
 *					 1 for division by 4
 *					 2 for division by 16
 *					 3 for division by 64
 */
#define BRGCLK_DIV_FACTOR  0

 
#undef BOOT_SET_BY_SERIAL
#define BOOT_SET_BY_SERIAL


#define INCLUDE_MOT_FEC          	/* define if you are using the FEC. */
#define INCLUDE_END                     /* define if you are using the FEC */



/* miscellaneous definitions */
 
#define NV_RAM_SIZE     NONE            /* no NVRAM */
 
/* Memory addresses */

#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* Base of RAM */
#define LOCAL_MEM_BANK_SIZE     (32*1024*1024)      /* size of each bank */
#define LOCAL_MEM_SENCOND_ADS   LOCAL_MEM_BANK_SIZE
 #define LOCAL_MEM_SIZE          (9*1024*1024)      /* 给vxWorks分配 9Mbyte memory */

/* Flash有2M, 0x1000 0000 -- 0x101F FFFF, 预留128M */
#define FLASH_A_BASE_ADDR       0x10000000          /*(256*1024*1024)*/     /* Base of Flash A */
#define FLASH_A_SIZE            (2*1024*1024)       /* 2 Mbyte */
#define FLASH_BASE_ADDR         FLASH_A_BASE_ADDR   /* Base of Flash */
#define FLASH_SIZE              FLASH_A_SIZE        /* 2 Mbyte */

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, and RAM_HIGH_ADRS are defined
 * in config.h, MakeSkel, Makefile, and Makefile.*
 * All definitions for these constants must be identical.
 */
 
 /* Bios 使用512K 0x1800 0000 -- 0x1807 FFFF, 不扩充 */
#define ROM_BASE_ADRS           0x18000000      /* base address of ROM */
#define ROM_TEXT_ADRS           (ROM_BASE_ADRS + 0x100)
#define ROM_SIZE                0x00080000      /* 512K ROM space */
/*2条32位指令 = 8bytes*/
#define ROM_VERSION_ADRS		(ROM_TEXT_ADRS + 8)

/* FPGA 使用地址16M 0x1900 0000 -- 0x19FF FFFF 预留128M*/
/* DSP 使用地址16M 0x2100 0000 -- 0x2100 0020 预留64M
 * 由于DSP是数据地址线复用的,地位地址线作为片选,译码,所以只用到32字节的地址空间
 */
 
/* RAM address for ROM boot */
#define RAM_HIGH_ADRS           (LOCAL_MEM_LOCAL_ADRS + 0x00E00000)
#define RAM_MID_ADRS         	(LOCAL_MEM_LOCAL_ADRS + 0x00480000) /* RAM address for compressed image */
#define RAM_LOW_ADRS            (LOCAL_MEM_LOCAL_ADRS + 0x00020000)

#define USER_RESERVED_MEM 0
/* Default power management mode - selected via vxPowerModeSet() in
 * sysHwInit().
 */

#define DEFAULT_POWER_MGT_MODE  VX_POWER_MODE_DISABLE


#define LED_RUN                         0x0001          /* PC15 */
#define LED_ALARM                       0x0004          /* PC13 */
#define LED_ALL                         0x0005          /* PC15 + PC13 */
#define LED_ON                          0x0
#define LED_OFF                         0x1
#define LED_FLASH						0x2

#define PCB_VER0                        0x4000              /* PA1 */
#define PCB_VER1                        0x10000             /* PB15 */
#define PCB_VER0_SHIFT                  14
#define PCB_VER1_SHIFT                  15

#define SELECT_DELAY 500


#define PAODRMASK	0x00fa

#define PBODRMASK	0x0000ffff
#define PBDATMASK	0x0003ffff
#define PBDIRMASK	0x0003ffff
#define PBPARMASK	0x0003ffff

#define PCDATMASK	0x0fff
#define PCDIRMASK	0x0fff
#define PCPARMASK	0x0fff
#define PCSOMASK	0x0ff3
#define PCINTMASK	0x0fff

#define PDDATMASK	0x1fff
#define PDDIRMASK	0x1fff
#define PDPARMASK	0x1fff

#define CACHE_CMD_WRITE_THROUGH 0x01000000    /* Write through mode */


#include "ads860.h"				/* include the ads860 params */



#endif	/* INCconfigh */
#if defined(PRJ_BUILD)
#include "prjParams.h"
#endif