ppc860sio.c

motorola mpc系列 mpc852cpu bsp

/************************************************************************
Copyright 2003 - 2004 UPTI, Inc.

filename     : ppc860Sio.c

description  : Motorola MPC800 SMC UART serial driver

author       : lx

modification : lx   create            2003-01-01
************************************************************************/

#include "copyright_wrs.h"

/*
DESCRIPTION
This is the driver for the SMCs in the internal Communications Processor (CP)
of the Motorola MPC68860/68821.  This driver only supports the SMCs in 
asynchronous UART mode.

USAGE
A PPC800SMC_CHAN structure is used to describe the chip.
The BSP's sysHwInit() routine typically calls sysSerialHwInit(),
which initializes all the values in the PPC860SMC_CHAN structure (except
the SIO_DRV_FUNCS) before calling ppc860DevInit().

The BSP's sysHwInit2() routine typically calls sysSerialHwInit2() which
connects the chip's interrupts via intConnect().

INCLUDE FILES: drv/sio/ppc860Sio.h
*/

/* includes */

#include "vxWorks.h"
#include "intLib.h"
#include "errno.h"
#include "sioLib.h"
#include "drv/multi/ppc860Siu.h"
#include "drv/multi/ppc860Cpm.h"
#include "drv/sio/ppc860Sio.h"

/* defines */

#define DEFAULT_BAUD 9600

/* forward declarations */

static STATUS ppc860Ioctl (PPC860SMC_CHAN *pChan,int request,int arg);
static void   ppc860ResetChannel (PPC860SMC_CHAN *pChan);
static int    ppc860PollOutput (SIO_CHAN *,char);
static int    ppc860PollInput (SIO_CHAN *,char *);
static void   ppc860Startup (PPC860SMC_CHAN *);
static int    ppc860CallbackInstall (SIO_CHAN *, int, STATUS (*)(), void *);

/* local driver function table */

static SIO_DRV_FUNCS ppc860SioDrvFuncs =
    {
    (int (*)())			ppc860Ioctl,
    (int (*)())			ppc860Startup,
    				ppc860CallbackInstall,
    (int (*)())			ppc860PollInput,
    (int (*)(SIO_CHAN *,char))	ppc860PollOutput
    };

/*******************************************************************************
*
* ppc860DevInit - initialize the SMC
*
* This routine is called to initialize the chip to a quiescent state.
* Note that the `smcNum' field of PPC860SMC_CHAN must be either 1 or 2.
*/

void ppc860DevInit
    (
    PPC860SMC_CHAN *pChan
    )
    {
    /* masks off this SMC's interrupt. */
	
    * CIMR(pChan->regBase) &= (~(CIMR_SMC1 >> (pChan->uart.smcNum - 1)));

    pChan->baudRate  = DEFAULT_BAUD;
    pChan->pDrvFuncs = &ppc860SioDrvFuncs;
    }

/*******************************************************************************
*
* ppc860ResetChannel - initialize the SMC
*/

static void ppc860ResetChannel 
    (
    PPC860SMC_CHAN *pChan
    )
    {
    int smc;			/* the SMC number being initialized */
    int baud;			/* the baud rate generator being used */
    int frame;

    int oldlevel = intLock ();	/* lock interrupts */ 

    smc  = pChan->uart.smcNum - 1;		/* get SMC number */
    baud = pChan->bgrNum - 1;			/* get BRG number */

    pChan->uart.intMask = CIMR_SMC1 >> smc;

    /* set up SMC as NMSI, select Baud Rate Generator */

    switch( baud ) 
	{
	default:	/* default to BRG1 */
	case 0: 
	    * SIMODE(pChan->regBase) |= (SIMODE_SMC1CS_BRG1 << (16 * smc));
	    break;
	case 1: 
	    * SIMODE(pChan->regBase) |= (SIMODE_SMC1CS_BRG2 << (16 * smc));
	    break;
	case 2: 
	    * SIMODE(pChan->regBase) |= (SIMODE_SMC1CS_BRG3 << (16 * smc));
	    break;
	case 3: 
	    * SIMODE(pChan->regBase) |= (SIMODE_SMC1CS_BRG4 << (16 * smc));
	    break;
        }
 
    /* reset baud rate generator, wait for reset to clear... */
 
    *pChan->pBaud |= BRGC_RST;
    while (*pChan->pBaud & BRGC_RST);

    ppc860Ioctl (pChan, SIO_BAUD_SET, pChan->baudRate);

    /* set up transmit buffer descriptors */

    pChan->uart.txBdBase = (SMC_BUF *) (pChan->regBase +
			 ((UINT32) pChan->uart.txBdBase ));
    pChan->uart.pSmc->param.tbase = (UINT16) ((UINT32) pChan->uart.txBdBase);
    pChan->uart.pSmc->param.tbptr = (UINT16) ((UINT32) pChan->uart.txBdBase);
    pChan->uart.txBdNext = 0;

    /* initialize each transmit buffer descriptor */

    for (frame = 0; frame < pChan->uart.txBdNum; frame++)
        {
        pChan->uart.txBdBase[frame].statusMode = BD_TX_INTERRUPT_BIT;

        pChan->uart.txBdBase[frame].dataPointer = pChan->uart.txBufBase +
                                                (frame * pChan->uart.txBufSize);
        }

    /* set the last BD to wrap to the first */

    pChan->uart.txBdBase[(frame - 1)].statusMode |= BD_TX_WRAP_BIT;

    /* set up receive buffer descriptors */

    pChan->uart.rxBdBase = (SMC_BUF *) (pChan->regBase +
		         ((UINT32) pChan->uart.rxBdBase ));

    pChan->uart.pSmc->param.rbase = (UINT16) ((UINT32) pChan->uart.rxBdBase);
    pChan->uart.pSmc->param.rbptr = (UINT16) ((UINT32) pChan->uart.rxBdBase);
    pChan->uart.rxBdNext = 0;

    /* initialize each receive buffer descriptor */
	
    for (frame = 0; frame < pChan->uart.rxBdNum; frame++)
        {
        pChan->uart.rxBdBase[frame].statusMode = BD_RX_EMPTY_BIT |
						 BD_RX_INTERRUPT_BIT;
        pChan->uart.rxBdBase[frame].dataLength = 1; /* char oriented */
        pChan->uart.rxBdBase[frame].dataPointer = pChan->uart.rxBufBase + frame;
        }

    /* set the last BD to wrap to the first */

    pChan->uart.rxBdBase[(frame - 1)].statusMode |= BD_RX_WRAP_BIT;

    /* set SMC attributes to standard UART mode */

    pChan->uart.pSmcReg->smcmr = SMCMR_STD_MODE;

    /* initialize parameter RAM area for this SMC */

    pChan->uart.pSmc->param.rfcr   = 0x18;	/* supervisor data access */
    pChan->uart.pSmc->param.tfcr   = 0x18;	/* supervisor data access */
    pChan->uart.pSmc->param.mrblr  = 0x1;	/* one character rx buffers */
    pChan->uart.pSmc->param.maxidl = 0x0;	/* no idle features */
    pChan->uart.pSmc->param.brkln  = 0x0;	/* no breaks received yet */
    pChan->uart.pSmc->param.brkec  = 0x0;	/* zero break condition ctr */
    pChan->uart.pSmc->param.brkcr  = 0x1;	/* xmit 1 BRK on stop */

    /* clear all events */

    pChan->uart.pSmcReg->smce = SMCE_ALL_EVENTS;

    /* enables the transmitter and receiver  */

    pChan->uart.pSmcReg->smcmr |= SMCMR_TEN | SMCMR_REN;

    /* unmask interrupt (Tx, Rx only) */

    pChan->uart.pSmcReg->smcm  = SMCM_TX_MSK | SMCM_RX_MSK;
    *CIMR(pChan->regBase) |= pChan->uart.intMask;

    intUnlock (oldlevel);			/* UNLOCK INTERRUPTS */
    }

/*******************************************************************************
*
* ppc860Ioctl - special device control
*
* RETURNS: OK on success, EIO on device error, ENOSYS on unsupported
*          request.
*
*/

LOCAL STATUS ppc860Ioctl
    (
    PPC860SMC_CHAN *	pChan,		/* device to control */
    int			request,	/* request code */
    int			arg		/* some argument */
    )
    {
    int		baudRate;
    int 	oldlevel;
    STATUS 	status = OK;

    switch (request)
	{
	case SIO_BAUD_SET:
            if (arg >=  50 && arg <= 38400)	/* could go higher... */
		{
		/* calculate proper counter value, then enable BRG */

		baudRate = (pChan->clockRate + (8 * arg)) / (16 * arg);

		if (--baudRate > 0xfff)
		    *pChan->pBaud = (BRGC_CD_MSK &
		    (((baudRate + 8) / 16) << BRGC_CD_SHIFT)) | BRGC_EN |
		    BRGC_DIV16;
                else
                    *pChan->pBaud = (BRGC_CD_MSK & 
			(baudRate << 1)) | BRGC_EN;

                pChan->baudRate = arg;
		}
            else
	        status = EIO;
	    break;
    
	case SIO_BAUD_GET:
	    * (int *) arg = pChan->baudRate;
	    break;

	case SIO_MODE_SET:
            if (!((int) arg == SIO_MODE_POLL || (int) arg == SIO_MODE_INT))
                {
                status = EIO;
                break;
                }

            /* lock interrupt  */

            oldlevel = intLock();

            /* initialize channel on first MODE_SET */

            if (!pChan->channelMode)
                ppc860ResetChannel(pChan);

            /*
             * if switching from POLL to INT mode, wait for all characters to
             * clear the output pins
             */

            if ((pChan->channelMode == SIO_MODE_POLL) && (arg == SIO_MODE_INT))
                {
		int i;

                for (i=0; i < pChan->uart.txBdNum; i++)
                    while (pChan->uart.txBdBase
                           [(pChan->uart.txBdNext + i) % pChan->uart.txBdNum].
                           statusMode & BD_TX_READY_BIT);

                }

            if (arg == SIO_MODE_INT)
		{
                * CISR(pChan->regBase) = pChan->uart.intMask;
				/* reset the SMC's interrupt status bit */

		* CIMR(pChan->regBase) |= pChan->uart.intMask;
				/* enable this SMC's interrupt  */

		pChan->uart.pSmcReg->smce = SMCE_RX;	
				/* reset the receiver status bit */ 

                pChan->uart.pSmcReg->smcm = SMCM_RX_MSK | SMCM_TX_MSK;
				/* enables receive and transmit interrupts */