pd6700.h

嵌入式linux 开发板驱动程序

#ifndef _LINUX_PD6700_H
#define _LINUX_PD6700_H

#define PD67_IDENT	0x00	/* Identification and revision */
#define PD67_STATUS	0x01	/* Interface status */
#define PD67_POWER	0x02	/* Power and RESETDRV control */
#define PD67_INTCTL	0x03	/* Interrupt and general control */
#define PD67_CSC	0x04	/* Card status change */
#define PD67_CSCINT	0x05	/* Card status change interrupt control */
#define PD67_MAP_ENA	0x06	/* Address window enable */
#define PD67_IOCTL	0x07	/* I/O control */

/* Offsets for I/O and memory window registers */
#define PD67_IO(map)	(0x08+((map)<<2))
#define PD67_MEM(map)	(0x10+((map)<<3))
#define PD67_W_START	0
#define PD67_W_STOP	2
#define PD67_W_OFF	4

#define PD67_MISC_CTL_1		0x16	/* Misc control 1 */
#define PD67_FIFO_CTL			0x17	/* FIFO control */
#define PD67_MISC_CTL_2		0x1E	/* Misc control 2 */
#define PD67_CHIP_INFO		0x1f	/* Chip information */
#define PD67_ATA_CTL			0x26	/* 6730: ATA control */
#define PD67_EXT_INDEX		0x2e	/* Extension index */
#define PD67_EXT_DATA			0x2f	/* Extension data */

#define PD67_SET_TIME0		0x3a
#define PD67_CMD_TIME0		0x3b
#define PD67_REC_TIME0		0x3c
#define PD67_SET_TIME1		0x3d
#define PD67_CMD_TIME1		0x3e
#define PD67_REC_TIME1		0x3f

/* Flags for PD67_STATUS */
#define PD67_CS_BVD1	0x01			// MEMORY模式，电池状态
#define PD67_CS_STSCHG	0x01		// IO 卡内部状态改变
#define PD67_CS_BVD2	0x02			// MEMORY模式，电池状态
#define PD67_CS_SPKR	0x02  		// IO 卡
#define PD67_CS_DETECT	0x0C		// 是插入检测
#define PD67_CS_WRPROT	0x10		// 写保护
#define PD67_CS_READY	0x20	/* Inverted */
#define PD67_CS_POWERON	0x40
#define PD67_CS_GPI	0x80

/* Flags for PD67_POWER */
#define PD67_PWR_OFF	0x00	/* Turn off the socket */
#define PD67_PWR_OUT	0x80	/* Output enable */
#define PD67_PWR_NORESET 0x40	/* Disable RESETDRV on resume */
#define PD67_PWR_AUTO	0x20	/* Auto pwr switch enable */
#define PD67_VCC_MASK	0x18	/* Mask for turning off Vcc */
/* There are different layouts for B-step and DF-step chips: the B
   step has independent Vpp1/Vpp2 control, and the DF step has only
   Vpp1 control, plus 3V control */
#define PD67_VCC_5V	0x10	/* Vcc = 5.0v */
#define PD67_VCC_3V	0x18	/* Vcc = 3.3v */
#define PD67_VPP2_MASK	0x0c	/* Mask for turning off Vpp2 */
#define PD67_VPP2_5V	0x04	/* Vpp2 = 5.0v */
#define PD67_VPP2_12V	0x08	/* Vpp2 = 12.0v */
#define PD67_VPP1_MASK	0x03	/* Mask for turning off Vpp1 */
#define PD67_VPP1_5V	0x01	/* Vpp2 = 5.0v */
#define PD67_VPP1_12V	0x02	/* Vpp2 = 12.0v */

/* Flags for PD67_INTCTL */
#define PD67_RING_ENA	0x80
#define PD67_PC_RESET	0x40
#define PD67_PC_IOCARD	0x20
#define PD67_INTR_ENA	0x10
#define PD67_IRQ_MASK	0x0F

/* Flags for PD67_CSC and PD67_CSCINT*/
#define PD67_CSC_BVD1	0x01
#define PD67_CSC_STSCHG	0x01
#define PD67_CSC_BVD2	0x02
#define PD67_CSC_READY	0x04
#define PD67_CSC_DETECT	0x08
#define PD67_CSC_ANY	0x0F
#define PD67_CSC_GPI	0x10

/* Flags for PD67_MAP_ENA */
#define PD67_ENA_IO(map)	(0x40 << (map))
#define PD67_ENA_MEM(map)	(0x01 << (map))

/* Flags for PD67_IOCTL */
#define PD67_IOCTL_MASK(map)		(0x0F << (map<<2))
#define PD67_IOCTL_WAIT(map)		(0x08 << (map<<2))
#define PD67_IOCTL_0WS(map)			(0x04 << (map<<2))
#define PD67_IOCTL_IOCS16(map)	(0x02 << (map<<2))
#define PD67_IOCTL_16BIT(map)		(0x01 << (map<<2))

/* PD6722 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_DATA_MASK0		0x01	/* Data mask 0 */
#define PD67_DATA_MASK1		0x02	/* Data mask 1 */
#define PD67_DMA_CTL			0x03	/* DMA control */

/* PD6730 extension registers -- indexed in PD67_EXT_INDEX */
#define PD67_EXT_CTL_1		0x03	/* Extension control 1 */
#define PD67_MEM_PAGE(n)	((n)+5)	/* PCI window bits 31:24 */
#define PD67_EXTERN_DATA	0x0a
#define PD67_MISC_CTL_3		0x25
#define PD67_SMB_PWR_CTL	0x26

/* I/O window address offset */
#define PD67_IO_OFF(w)		(0x36+((w)<<1))

/* Timing register sets */
#define PD67_TIME_SETUP(n)	(0x3a + 3*(n))
#define PD67_TIME_CMD(n)		(0x3b + 3*(n))
#define PD67_TIME_RECOV(n)	(0x3c + 3*(n))

/* Flags for PD67_MISC_CTL_1 */
#define PD67_MC1_5V_DET			0x01	/* 5v detect */
#define PD67_MC1_MEDIA_ENA	0x01	/* 6730: Multimedia enable */
#define PD67_MC1_VCC_3V			0x02	/* 3.3v Vcc */
#define PD67_MC1_PULSE_MGMT	0x04
#define PD67_MC1_PULSE_IRQ	0x08
#define PD67_MC1_SPKR_ENA		0x10
#define PD67_MC1_INPACK_ENA	0x80

/* Flags for PD67_FIFO_CTL */
#define PD67_FIFO_EMPTY			0x80

/* Flags for PD67_MISC_CTL_2 */
#define PD67_MC2_FREQ_BYPASS	0x01
#define PD67_MC2_DYNAMIC_MODE	0x02
#define PD67_MC2_SUSPEND			0x04
#define PD67_MC2_5V_CORE			0x08
#define PD67_MC2_LED_ENA			0x10	/* IRQ 12 is LED enable */
#define PD67_MC2_FAST_PCI			0x10	/* 6729: PCI bus > 25 MHz */
#define PD67_MC2_3STATE_BIT7	0x20	/* Floppy change bit */
#define PD67_MC2_DMA_MODE			0x40
#define PD67_MC2_IRQ15_RI			0x80	/* IRQ 15 is ring enable */

/* Flags for PD67_CHIP_INFO */
#define PD67_INFO_SLOTS				0x20	/* 0 = 1 slot, 1 = 2 slots */
#define PD67_INFO_CHIP_ID			0xc0
#define PD67_INFO_REV					0x1c

/* Fields in PD67_TIME_* registers */
#define PD67_TIME_SCALE				0xc0
#define PD67_TIME_SCALE_1			0x00
#define PD67_TIME_SCALE_16		0x40
#define PD67_TIME_SCALE_256		0x80
#define PD67_TIME_SCALE_4096	0xc0
#define PD67_TIME_MULT				0x3f

/* Fields in PD67_DMA_CTL */
#define PD67_DMA_MODE					0xc0
#define PD67_DMA_OFF					0x00
#define PD67_DMA_DREQ_INPACK	0x40
#define PD67_DMA_DREQ_WP			0x80
#define PD67_DMA_DREQ_BVD2		0xc0
#define PD67_DMA_PULLUP				0x20	/* Disable socket pullups? */

/* Flags for memory window registers */
#define PD67_MEM_16BIT	0x8000	/* In memory start high byte */
#define PD67_MEM_0WS	0x4000
#define PD67_MEM_WS1	0x8000	/* In memory stop high byte */
#define PD67_MEM_WS0	0x4000
#define PD67_MEM_WRPROT	0x8000	/* In offset high byte */
#define PD67_MEM_REG	0x4000

#define PD67_REG(slot, reg)	(((slot) << 6) + reg)


#endif