📄 wmplatform_raw.h
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# define FPGA_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + FPGA_OFFSET)
# define DMA_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + DMAC_OFFSET)
# define SSP2_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + SSP2_OFFSET)
# define I2C_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + I2C_OFFSET)
# define I2S_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + I2S_OFFSET)
#else /* PALM_DBPXA250 */
# define VOLATILE_INTC_T volatile XLLP_INTC_T
# define VOLATILE_AC97_T volatile XLLP_AC97_T
# define VOLATILE_GPIO_T volatile XLLP_GPIO_T
# define VOLATILE_OST_T volatile XLLP_OST_T
# define VOLATILE_CLKMGR_T volatile XLLP_CLKMGR_T
# define VOLATILE_BCR_T volatile XLLP_BCR_T
# define VOLATILE_DMAC_T volatile XLLP_DMAC_T
# define VOLATILE_SSP_T volatile XLLP_SSP_REGS
# define VOLATILE_I2C_T volatile XLLP_I2C_T
# define VOLATILE_I2S_T volatile XLLP_I2S_T
# if defined ( WM_BSP_MAINSTONEII ) || defined( WM_BSP_INTEL_DBPXA27X ) || defined ( WM_BSP_MAINSTONEIII )
# define AC97_REGS_PHYSICAL BULVERDE_BASE_REG_PA_AC97
# define GPIO_REGS_PHYSICAL BULVERDE_BASE_REG_PA_GPIO
# define OST_REGS_PHYSICAL BULVERDE_BASE_REG_PA_OST
# define INTC_REGS_PHYSICAL BULVERDE_BASE_REG_PA_INTC
# define CLKMGR_REGS_PHYSICAL BULVERDE_BASE_REG_PA_CLKMGR
# define FPGA_REGS_PHYSICAL MAINSTONEII_BASE_REG_PA_FPGA
# define DMA_REGS_PHYSICAL BULVERDE_BASE_REG_PA_DMAC
# define SSP2_REGS_PHYSICAL BULVERDE_BASE_REG_PA_SSP2
# define I2C_REGS_PHYSICAL BULVERDE_BASE_REG_PA_I2C
# define I2S_REGS_PHYSICAL BULVERDE_BASE_REG_PA_I2S
# else /* WM_BSP_MAINSTONEII || WM_BSP_INTEL_DBPXA27X || WM_BSP_MAINSTONEIII */
# define AC97_REGS_PHYSICAL AC97_BASE_PHYSICAL
# define GPIO_REGS_PHYSICAL GPIO_BASE_PHYSICAL
# define OST_REGS_PHYSICAL OST_BASE_PHYSICAL
# define INTC_REGS_PHYSICAL INTC_BASE_PHYSICAL
# define CLKMGR_REGS_PHYSICAL CLK_BASE_PHYSICAL
# define FPGA_REGS_PHYSICAL FPGA_REGS_BASE_PHYSICAL
# define DMA_REGS_PHYSICAL DMAC_BASE_PHYSICAL
# define SSP2_REGS_PHYSICAL SSP2_BASE_PHYSICAL
# define I2C_REGS_PHYSICAL I2C_BASE_PHYSICAL
# define I2S_REGS_PHYSICAL I2S_BASE_PHYSICAL
# define AC97_REGS_VIRTUAL AC97_BASE_U_VIRTUAL
# define GPIO_REGS_VIRTUAL GPIO_BASE_U_VIRTUAL
# define OST_REGS_VIRTUAL OST_BASE_U_VIRTUAL
# define INTC_REGS_VIRTUAL INTC_BASE_U_VIRTUAL
# define CLKMGR_REGS_VIRTUAL CLK_BASE_U_VIRTUAL
# define FPGA_REGS_VIRTUAL FPGA_REGS_BASE_U_VIRTUAL
# define DMA_REGS_VIRTUAL DMAC_BASE_U_VIRTUAL
# define SSP2_REGS_VIRTUAL SSP2_BASE_U_VIRTUAL
# define I2C_REGS_VIRTUAL I2C_BASE_U_VIRTUAL
# define I2S_REGS_VIRTUAL I2S_BASE_U_VIRTUAL
# endif /* WM_BSP_MAINSTONEII || WM_BSP_INTEL_DBPXA27X || WM_BSP_MAINSTONEIII */
#endif /* PALM_DBPXA250 */
/*
* AC Link controller definitions.
*/
/* mask definitions for the Global Control Register */
#define AC97GCR_GIE 0x00000001
#define AC97GCR_ColdReset 0x00000002
#define AC97GCR_WarmReset 0x00000004
#define AC97GCR_AclinkOff 0x00000008
/* mask definitions for the CodecAccessRegister */
#define AC97CAR_CAIP 0x00000001
/* mask definitions for the Global Status Register */
#define AC97GSR_CDONE (0x00000001 << 19)
#define AC97GSR_SDONE (0x00000001 << 18)
#define AC97_SEC_RESUME_INTR (0x00000001 << 11)
#define AC97_PRI_RESUME_INTR (0x00000001 << 10)
#define AC97GSR_READ_COMPLETION_STATUS (0x00000001 << 15)
#define AC97GSR_CODEC0_READY (0x00000001 << 8)
#define AC97GSR_CODEC1_READY (0x00000001 << 9)
#define AC97GSR_CODEC_READY (AC97GSR_CODEC0_READY | AC97GSR_CODEC1_READY)
#ifndef XLLP_SSCR0_DSS_17BIT
# define XLLP_SSCR0_DSS_17BIT ( XLLP_SSCR0_EDSS | 0 )
#endif
#ifndef XLLP_SACR0_RFTH_VAL
# define XLLP_SACR0_RFTH_VAL(_thresh) ( ((_thresh) & 0xF ) << 12 )
#endif
#ifndef XLLP_SACR0_TFTH_VAL
# define XLLP_SACR0_TFTH_VAL(_thresh) ( ((_thresh) & 0xF ) << 8 )
#endif
/*
* Useful FIFO definitions.
*/
#define AC97_FIFO_DEPTH 16
#define I2S_OUTPUT_FIFO_DEPTH 1
#define I2S_INPUT_FIFO_DEPTH 14
#if WM_BOARD_MAINSTONEII
# define AC97_RXFIFO_SERVICE_REQUEST 0x00000004
# define AC97_RXFIFO_ENDOFCHAIN 0x00000008
#endif
#define AC97_RXFIFO_ERROR 0x00000010
#define DMAC_AC97_AUDIO_RCV_FIFO 0x40500040
#define DMAC_AC97_AUDIO_XMIT_FIFO 0x40500040
#define DMAC_AC97_MODEM_RCV_FIFO 0x40500140
#define DMAC_AC97_MODEM_XMIT_FIFO 0x40500140
#define DMAC_AC97_MONO_XMIT_FIFO DMAC_AC97_MODEM_XMIT_FIFO
#define DMAC_AC97_AUDIO_MIC_FIFO 0x40500060
#define DMAC_I2S_AUDIO_RCV_FIFO 0x40400080
#define DMAC_I2S_AUDIO_XMIT_FIFO 0x40400080
#define DMAC_SSP1_AUDIO_RCV_FIFO 0x41000010
#define DMAC_SSP1_AUDIO_XMIT_FIFO 0x41000010
#define DMAC_SSP2_AUDIO_RCV_FIFO 0x41700010
#define DMAC_SSP2_AUDIO_XMIT_FIFO 0x41700010
#define DMAC_SSP3_AUDIO_RCV_FIFO 0x41900010
#define DMAC_SSP3_AUDIO_XMIT_FIFO 0x41900010
/*
* Maximum burst size of each data transfer.
*/
#define DMAC_BURST_SIZE_8_BYTES 0x1
#define DMAC_BURST_SIZE_16_BYTES 0x2
#define DMAC_BURST_SIZE_32_BYTES 0x3
/*
* Interrupt definitions.
*/
/* mask definitions for Interrupt Control Registers' OSMR
*(Operating System Match Reg 1) bit */
#ifndef ICMR_OSMR1
# define ICMR_OSMR1 0x08000000
#endif
/*
* DMA definitions.
*/
#define DCSR_BUSERRINTR (0x1U << 0) /* Bus error status bit */
#define DCSR_STARTINTR (0x1U << 1) /* Descriptor fetch status */
#define DCSR_ENDINTR (0x1U << 2) /* finish status */
#define DCSR_STOPINTR (0x1U << 3) /* stopped status */
#define DCSR_REQPEND (0x1U << 8) /* Request Pending (read-only) */
#define DCSR_STARTIRQEN (0x1U << 21) /* Enable the start interrupt (when the descriptor is loaded) */
#define DCSR_STOPIRQEN (0x1U << 29) /* Enable the stopped interrupt (when the descriptor is done) */
#define DCSR_NOFETCH (0x1U << 30) /* Descriptor fetch mode, 0 = fetch */
#ifndef DCSR_RUN
# define DCSR_RUN (0x1U << 31) /* run, 1=start */
#endif
#define DMA_MAP_VALID_MASK (0x1U << 7) /* Request is mapped to a valid channel
indicated by DRCMRx(3:0) */
#define DCSR_DMA_INT_MASK (DCSR_BUSERRINTR | \
DCSR_STARTINTR | \
DCSR_ENDINTR | \
DCSR_STOPINTR)
/*
* The DMA channels.
*/
#if XLLP_AVAILABLE
# define DMA_CHAN_AC97_STEREO_OUT XLLP_DMAC_AC97_AUDIO_TX
# define DMA_CHAN_AC97_STEREO_IN XLLP_DMAC_AC97_AUDIO_RX
# define DMA_CHAN_AC97_MODEM_OUT XLLP_DMAC_AC97_MODEM_TX
# define DMA_CHAN_AC97_MONO_OUT DMA_CHAN_AC97_MODEM_OUT
# define DMA_CHAN_AC97_MODEM_IN XLLP_DMAC_AC97_MODEM_RX
# define DMA_CHAN_AC97_MIC XLLP_DMAC_AC97_MIC
# define DMA_CHAN_I2S_STEREO_OUT XLLP_DMAC_I2S_TX
# define DMA_CHAN_I2S_STEREO_IN XLLP_DMAC_I2S_RX
# define DMA_CHAN_VOICE_OUT XLLP_DMAC_SSP_2_TX
# define DMA_CHAN_VOICE_IN XLLP_DMAC_SSP_2_RX
#else /* XLLP_AVAILABLE */
# define DMA_CHAN_AC97_STEREO_OUT 12
# define DMA_CHAN_AC97_STEREO_IN 11
# define DMA_CHAN_AC97_MODEM_OUT 10
# define DMA_CHAN_AC97_MONO_OUT DMA_CHAN_AC97_MODEM_OUT
# define DMA_CHAN_AC97_MODEM_IN 9
# define DMA_CHAN_AC97_MIC 8
# define DMA_CHAN_I2S_STEREO_OUT 3
# define DMA_CHAN_I2S_STEREO_IN 2
# define DMA_CHAN_VOICE_OUT 16
# define DMA_CHAN_VOICE_IN 15
#endif /* XLLP_AVAILABLE */
/*
* Size of a DMA Descriptor.
*/
#define WMAUDIO_DMA_DESC_SIZE 0x20
/*
* Size of a DMA Buffer.
*/
#ifndef AUDIO_BUFFER_SIZE
# define AUDIO_BUFFER_SIZE 0x1000
#endif
/*
* Audio DMA buffer and descriptor definitions.
*/
#define WMDMA_BUFFER_BASE_PHYSICAL DMA_XMIT_A_BUFFER_BASE_PHYSICAL
#define WMDMA_BUFFER_BASE_VIRTUAL DMA_XMIT_A_BUFFER_BASE_VIRTUAL
#define WMDMA_DESCRIPTOR_BASE_PHYSICAL DMA_XMIT_A_DESCRIPTOR_BASE_PHYSICAL
#define WMDMA_DESCRIPTOR_BASE_VIRTUAL DMA_XMIT_A_DESCRIPTOR_BASE_VIRTUAL
/*
* Decode the DCMD register.
*/
struct dcmdRegBits
{
unsigned len :13;
unsigned rsv0 :1;
unsigned width :2;
unsigned size :2;
unsigned endian :1;
unsigned flybyt :1;
unsigned flybys :1;
unsigned endirqen :1;
unsigned startirqen :1;
unsigned rsv1 :5;
unsigned flowtrg :1;
unsigned flowsrc :1;
unsigned inctrgadd :1;
unsigned incsrcadd :1;
};
/*
* A union to allow bitfields or the full value.
*/
union DmaCmdReg
{
volatile struct dcmdRegBits DcmdReg;
volatile XLLP_UINT32_T DcmdDword;
} ;
/*
* Mask for the length in the DCMD register
*/
#define WMAUDIO_DCMD_LEN_MASK 0x1FFF
/*
* Fix up XLLP typos.
*/
#if XLLP_AVAILABLE
/* From xllp_gpio.h */
# ifndef XLLP_GPIO_BIT_SSP2_SSPRXD2
# define XLLP_GPIO_BIT_SSP2_SSPRXD2 XXLP_GPIO_BIT_SSP2_SSPRXD2
# endif /* XLLP GPIO definitions */
/* From xllp_ssp.h */
# ifndef XLLP_SSCR1_TSRE
# define XLLP_SSCR1_TSRE XXLP_SSCR1_TSRE
# define XLLP_SSCR1_RSRE XXLP_SSCR1_RSRE
# define XLLP_SSCR1_TINTE XXLP_SSCR1_TINTE
# define XLLP_SSCR1_PINTE XXLP_SSCR1_PINTE
# define XLLP_SSCR1_STRF XXLP_SSCR1_STRF
# define XLLP_SSCR1_EFWR XXLP_SSCR1_EFWR
# define XLLP_SSCR1_MWDS XXLP_SSCR1_MWDS
# define XLLP_SSCR1_SPH XXLP_SSCR1_SPH
# define XLLP_SSCR1_LBM XXLP_SSCR1_LBM
# define XLLP_SSCR1_TIE XXLP_SSCR1_TIE
# define XLLP_SSCR1_RIE XXLP_SSCR1_RIE
# define XLLP_SSSP_BCE XXLP_SSSP_BCE
# define XLLP_SSSP_CSS XXLP_SSSP_CSS
# define XLLP_SSSP_TUR XXLP_SSSP_TUR
# define XLLP_SSSP_EOC XXLP_SSSP_EOC
# define XLLP_SSSP_TINT XXLP_SSSP_TINT
# define XLLP_SSSP_PINT XXLP_SSSP_PINT
# define XLLP_SSSP_RFL_MASK XXLP_SSSP_RFL_MASK
# define XLLP_SSSP_TFL_MASK XXLP_SSSP_TFL_MASK
# define XLLP_SSSP_ROR XXLP_SSSP_ROR
# define XLLP_SSSP_RFS XXLP_SSSP_RFS
# define XLLP_SSSP_TFS XXLP_SSSP_TFS
# define XLLP_SSSP_BSY XXLP_SSSP_BSY
# define XLLP_SSSP_RNE XXLP_SSSP_RNE
# define XLLP_SSSP_TNF XXLP_SSSP_TNF
# endif /* XLLP SSP definitions */
#endif /* XLLP_AVAILABLE */
/* I2S Controller sample rates */
#define WM_I2S_8K 72 /* 1001000 => 513.25kHz BITCLK => 8.019kHz */
#define WM_I2S_11K025 52 /* 0110100 => 702.75kHz BITCLK => 10.980kHz */
#define WM_I2S_16K 36 /* 0100100 => 1.026MHz BITCLK => 16.036kHz */
#define WM_I2S_22K05 26 /* 0011010 => 1.405MHz BITCLK => 21.953kHz */
#define WM_I2S_44K1 13 /* 0001101 => 2.836MHz BITCLK => 44.318kHz */
#define WM_I2S_48K 12 /* 0001100 => 3.058MHz BITCLK => 47.794kHz */
/*
* Function prototypes
*/
#ifdef __cplusplus
extern "C" {
#endif
#include "WMDeviceContext.h"
#if XLLP_AVAILABLE
/*-----------------------------------------------------------------------------
* Function: XllpStatusToWMStatus
*
* Convert an XLLP_STATUS_T to a WMSTATUS.
*
* Parameters:
* xllpStatus the XLLP_STATUS_T to convert.
*
* Returns: WMSTATUS
* The corresponding Wolfson status value.
*---------------------------------------------------------------------------*/
WMSTATUS XllpStatusToWMStatus( XLLP_STATUS_T xllpStatus );
#endif /* XLLP_AVAILABLE */
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* __WMPLATFORM_RAW_H__ */
/*------------------------------ END OF FILE ---------------------------------*/
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