📄 wmplatform_raw.h
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# define WM_OUTPUT_TO_HEX_LEDS(_ctx, _value)\
_ctx->v_pBLRegs->hex_led = (_value)
#elif WM_BOARD_MAINSTONEII
/*
* Touch definitions for Mainstone II.
*/
# define WM_CLEAR_PEN_DETECT_INTERRUPT(_ctx)\
_ctx->v_pBLRegs->PSCR1 &= ~GPIO_BIT(PEN_DETECT_GPIO_NUM)
# define WM_CONFIGURE_PEN_DETECT_INTERRUPT(_ctx)\
((void)0)
# define WM_SET_PEN_DETECT_INTERRUPT_ACTIVE_HIGH(_ctx)\
((void)0)
# define WM_SET_PEN_DETECT_INTERRUPT_ACTIVE_LOW(_ctx)\
((void)0)
# define WM_CLEAR_PEN_DETECT_INTERRUPT_ACTIVE_HIGH(_ctx)\
((void)0)
# define WM_CLEAR_PEN_DETECT_INTERRUPT_ACTIVE_LOW(_ctx)\
((void)0)
# define WM_CLEAR_VIRTUAL_PEN_DETECT_INTERRUPT(_ctx)\
(void)0)
#if WM_MAINSTONEII_AMP_CONTROL
# define WM97_TURN_OFF_AMPLIFER_1(_ctx)\
_ctx->v_pBLRegs->MISCWR2 |= XLLP_BCR_MISCWR2_LINE1_SPKROFF
# define WM97_TURN_OFF_AMPLIFER_2(_ctx)\
_ctx->v_pBLRegs->MISCWR2 |= XLLP_BCR_MISCWR2_LINE2_SPKROFF
# define WM97_TURN_ON_AMPLIFER_1(_ctx)\
_ctx->v_pBLRegs->MISCWR2 &= ~XLLP_BCR_MISCWR2_LINE1_SPKROFF
# define WM97_TURN_ON_AMPLIFER_2(_ctx)\
_ctx->v_pBLRegs->MISCWR2 &= ~XLLP_BCR_MISCWR2_LINE2_SPKROFF
#else
# define WM97_TURN_OFF_AMPLIFER_1(_ctx)\
((void)0)
# define WM97_TURN_OFF_AMPLIFER_2(_ctx)\
((void)0)
# define WM97_TURN_ON_AMPLIFER_1(_ctx)\
((void)0)
# define WM97_TURN_ON_AMPLIFER_2(_ctx)\
((void)0)
#endif
/*
* USB On The Go (OTG) definitions for Mainstone II.
*/
# define USB_OTG_ENABLE(_ctx)\
_ctx->v_pBLRegs->MISCWR2 |= XLLP_BCR_MISCWR2_USB_OTG_SEL
# define USB_OTG_DISABLE(_ctx)\
_ctx->v_pBLRegs->MISCWR2 &= ~XLLP_BCR_MISCWR2_USB_OTG_SEL
# define USB_OTG_ENABLE_EXTERNAL_TRANSCEIVER(_ctx)\
_ctx->v_pBLRegs->MISCWR2 |= XLLP_BCR_MISCWR2_USB_OTG_RST
# define USB_OTG_DISABLE_EXTERNAL_TRANSCEIVER(_ctx)\
_ctx->v_pBLRegs->MISCWR2 &= ~XLLP_BCR_MISCWR2_USB_OTG_RST
/*
* SSP Mux definitions for Mainstone II.
*/
# ifndef XLLP_BCR_MISCWR3_SSP_MUX_SEL
# define XLLP_BCR_MISCWR3_SSP_MUX_SEL (XLLP_BIT_3)
# endif
# define SSP_MUX_USE_USB(_ctx)\
_ctx->v_pBLRegs->MISCWR3 |= XLLP_BCR_MISCWR3_SSP_MUX_SEL
# define SSP_MUX_USE_FFUART(_ctx)\
_ctx->v_pBLRegs->MISCWR3 &= ~XLLP_BCR_MISCWR3_SSP_MUX_SEL
/*
* HEX LED defines
*/
# define WM_OUTPUT_TO_HEX_LEDS(_ctx, _value)\
_ctx->v_pBLRegs->HLDR1 = (_value)
#endif
/*
* Platform translation of things which have different names but are
* really the same thing for our purposes.
*/
#if !XLLP_AVAILABLE
# define POCR pocr
# define PICR picr
# define MCCR mccr
# define GCR gcr
# define POSR posr
# define PISR pisr
# define MCSR mcsr
# define GSR gsr
# define CAR car
# define PCDR pcdr
# define MCDR mcdr
# define MOCR mocr
# define MICR micr
# define MOSR mosr
# define MISR misr
# define MODR modr
# define CodecRegsPrimaryAud v_pCodecBaseAddr
# define XLLP_INTC_T INTC_REGS
# define XLLP_AC97_T AC97_REGS
# define XLLP_I2C_T I2C_REGS
# define XLLP_I2S_T I2S_REGS
# define XLLP_GPIO_T GPIO_REGS
# define XLLP_OST_T OST_REGS
# define XLLP_CLKMGR_T CLKMAN_REGS
# define XLLP_BCR_T BLR_REGS
# define oscr0 oscr
# define XLLP_INTC_GPIOXX_2 INTC_GPIO80_2
# define XLLP_OST_TICKS_US (0x384 / 0x100)
# define XLLP_OST_TICKS_MS (0x384000 / 1000)
# define XLLP_UINT32_T unsigned int
# define XLLP_VUINT32_T volatile XLLP_UINT32_T
# define DMAC_DESC_FIELD_T unsigned long
# define XLLP_AC97_GSR_GSCI_MSK (0x1U << 0)
# define XLLP_AC97_GCR_GIE_MSK (0x1U << 0)
/* DMA */
# define XLLP_DMAC_T DMAC_REGS
# define DDG ddg
# define DRCMR drcmr
# define DCSR dcsr
# define DINT dint
# define DRCMR1 DRCMR
# define XLLP_INTC_DMAC (0x1U << 25)
/* I2S */
# define SACR0 sacr0
# define SACR1 sacr1
# define SASR0 sasr0
# define SAIMR saimr
# define SAICR saicr
# define SAITR saitr
# define SADIV sadiv
# define SADR sadr
/* I2S - SACR0 Pin Names */
# define XLLP_SACR0_ENB (1U << 0)
# define XLLP_SACR0_BCKD (1U << 2)
# define XLLP_SACR0_RST (1U << 3)
# define XLLP_SACR0_EFWR (1U << 4)
# define XLLP_SACR0_STRF (1U << 5)
/* I2S - SACR1 Pin Names */
# define XLLP_SACR1_AMSL (1U << 0)
# define XLLP_SACR1_DREC (1U << 3)
# define XLLP_SACR1_DRPL (1U << 4)
# define XLLP_SACR1_ENLBF (1U << 5)
/* I2S - SASR0 Pin Names */
# define XLLP_SASR0_TNF (1U << 0)
# define XLLP_SASR0_RNE (1U << 1)
# define XLLP_SASR0_BSY (1U << 2)
# define XLLP_SASR0_TFS (1U << 3)
# define XLLP_SASR0_RFS (1U << 4)
# define XLLP_SASR0_TUR (1U << 5)
# define XLLP_SASR0_ROR (1U << 6)
/* I2S - SAICR Pin Names */
# define XLLP_SAICR_TUR (1U << 5)
# define XLLP_SAICR_ROR (1U << 6)
/* I2S - SAIMR Pin Names */
# define XLLP_SAIMR_TFS (1U << 3)
# define XLLP_SAIMR_RFS (1U << 4)
# define XLLP_SAIMR_TUR (1U << 5)
# define XLLP_SAIMR_ROR (1U << 6)
# ifdef PALM_DBPXA250
/* DMA */
# define XLLP_DMAC_CHANNEL_T UInt32
# define XLLP_DMAC_DRCMR_T UInt32
/* OSSR Bits */
# define XLLP_OSSR_M0 (0x1 << 0)
# define XLLP_OSSR_M1 (0x1 << 1)
# define XLLP_OSSR_M2 (0x1 << 2)
# define XLLP_OSSR_M3 (0x1 << 3)
# define XLLP_OSSR_M4 (0x1 << 4)
# define XLLP_OSSR_M5 (0x1 << 5)
# define XLLP_OSSR_M6 (0x1 << 6)
# define XLLP_OSSR_M7 (0x1 << 7)
# define XLLP_OSSR_M8 (0x1 << 8)
# define XLLP_OSSR_M9 (0x1 << 9)
# define XLLP_OSSR_M10 (0x1 << 10)
# define XLLP_OSSR_M11 (0x1 << 11)
# define XLLP_OSSR_RESERVED_BITS (0xFFFFF000)
/* OIER Bits */
# define XLLP_OIER_E0 (0x1 << 0)
# define XLLP_OIER_E1 (0x1 << 1)
# define XLLP_OIER_E2 (0x1 << 2)
# define XLLP_OIER_E3 (0x1 << 3)
# define XLLP_OIER_E4 (0x1 << 4)
# define XLLP_OIER_E5 (0x1 << 5)
# define XLLP_OIER_E6 (0x1 << 6)
# define XLLP_OIER_E7 (0x1 << 7)
# define XLLP_OIER_E8 (0x1 << 8)
# define XLLP_OIER_E9 (0x1 << 9)
# define XLLP_OIER_E10 (0x1 << 10)
# define XLLP_OIER_E11 (0x1 << 11)
# define XLLP_OIER_RESERVED_BITS (0xFFFFF000)
/* GPIO registers */
# define GPLR gplr
# define GPDR gpdr
# define GPSR gpsr
# define GPCR gpcr
# define GRER grer
# define GFER gfer
# define GEDR gedr
# define GAFR gafr
/* Clocks */
# define XLLP_CLKEN_AC97 AC97_CE
# define XLLP_CLKEN_SSP2 SSP_CE
# define XLLP_CLKEN_I2S I2S_CE
# define XLLP_CLKEN_I2C I2C_CE
# else /* PALM_DBPXA250 */
# define XLLP_OIER_E1 OIER_E1
# define XLLP_OSSR_M1 OSSR_M1
# define XLLP_DMAC_DESCRIPTOR_T DMADescriptorChannelType
# define XLLP_DMAC_CHANNEL_T int
# define XLLP_DMAC_DRCMR_T int
# define DDADR ddadr
# define DSADR dsadr
# define DTADR dtadr
# define DCMD dcmd
/* Clocks */
# define XLLP_CLKEN_AC97 CLK_AC97
# define XLLP_CLKEN_SSP2 CLK_SSP
# define XLLP_CLKEN_I2S CLK_I2S
# define XLLP_CLKEN_I2C CLK_I2C
/* DMA array constants */
# define XLLP_DMAC_CHANNEL_NUM 16
# define XLLP_DMAC_DRCMR1_NUM 40
/* GPIO registers */
# define GPLR0 GPLR_x
# define GPLR1 GPLR_y
# define GPLR2 GPLR_z
# define GPDR0 GPDR_x
# define GPDR1 GPDR_y
# define GPDR2 GPDR_z
# define GPSR0 GPSR_x
# define GPSR1 GPSR_y
# define GPSR2 GPSR_z
# define GPCR0 GPCR_x
# define GPCR1 GPCR_y
# define GPCR2 GPCR_z
# define GRER0 GRER_x
# define GRER1 GRER_y
# define GRER2 GRER_z
# define GFER0 GFER_x
# define GFER1 GFER_y
# define GFER2 GFER_z
# define GEDR0 GEDR_x
# define GEDR1 GEDR_y
# define GEDR2 GEDR_z
# define GAFR0_L GAFR0_x
# define GAFR0_U GAFR1_x
# define GAFR1_L GAFR0_y
# define GAFR1_U GAFR1_y
# define GAFR2_L GAFR0_z
# define GAFR2_U GAFR1_z
# endif /* PALM_DBPXA250 */
#else /* XLLP_AVAILABLE */
# define DMAC_DESC_FIELD_T XLLP_UINT32_T
#endif /* XLLP_AVAILABLE */
#ifdef PALM_DBPXA250
# define VOLATILE_INTC_T XLLP_INTC_T
# define VOLATILE_AC97_T XLLP_AC97_T
# define VOLATILE_GPIO_T XLLP_GPIO_T
# define VOLATILE_OST_T XLLP_OST_T
# define VOLATILE_CLKMGR_T XLLP_CLKMGR_T
# define VOLATILE_BCR_T XLLP_BCR_T
# define VOLATILE_SSP_T XLLP_SSP_REGS
# define VOLATILE_I2C_T XLLP_I2C_T
# define VOLATILE_I2S_T XLLP_I2S_T
# define AC97_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + AC97_OFFSET)
# define GPIO_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + GPIO_OFFSET)
# define OST_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + OST_OFFSET)
# define INTC_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + INTC_OFFSET)
# define CLKMGR_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + CLK_OFFSET)
# define FPGA_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + FPGA_OFFSET)
# define DMA_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + DMAC_OFFSET)
# define SSP2_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + SSP2_OFFSET)
# define I2C_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + I2C_OFFSET)
# define I2S_REGS_PHYSICAL (PXA_PERIF_BASE_PHYSICAL + I2S_OFFSET)
# define AC97_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + AC97_OFFSET)
# define GPIO_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + GPIO_OFFSET)
# define OST_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + OST_OFFSET)
# define INTC_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + INTC_OFFSET)
# define CLKMGR_REGS_VIRTUAL (PXA_PERIF_BASE_VIRTUAL + CLK_OFFSET)
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